Dynamic power management in a processor design

An information handling system comprising:

• one or more processors;
• one or more pipelines included in the processors, each of the one or more pipelines including a plurality of pipeline stages;
• a memory accessible by the processors;
• one or more nonvolatile storage devices accessible by the processors;
• and
• a power management tool for gating off clocks, the power management tool being effective to:
• detect a stall condition within a selected pipeline stage from the plurality of pipeline stages, wherein the selected pipeline stage includes a first register, a second register, a first fill detector, and a second fill detector, the first fill detector controlling the first register and the second fill detector controlling the second register;
• activate a stall signal to the first fill detector in response to detecting the stall condition;
• in response to receiving the activated stall signal, wait until the first register includes a first instruction and gating off a first clock to the first register using the first fill detector once the first register includes the first instruction;
• after gating off the first clock, send a first register loaded signal from the first fill detector to the second fill detector;
• and
• in response to receiving the first register loaded signal, wait until the second register includes a second instruction and gating off a second clock to the second register using the second fill detector once the second register includes the second instruction.