Thermal throttle control with minimal impact to interrupt latency

A data processing system comprising:

• a bus;
• a memory coupled to the bus, wherein the memory includes a set of instructions;
• and
• a integrated circuit coupled to the bus, wherein the integrated circuit executes the set of instructions to monitor a setting of an interrupt status bit in a thermal sensor interrupt status register;
• setting the interrupt status bit when a temperature value in a thermal sensor current temperature status register for a sensor is greater than or equal to one of a corresponding sensor interrupt temperature value in a thermal sensor interrupt temperature register and a global interrupt temperature value in a thermal sensor global interrupt temperature register;
• determining whether to clear the interrupt status bit at a beginning of an interrupt handler routine;
• responsive to a determination to clear the interrupt status bit at a beginning of the interrupt handler routine, selecting one of handling the interrupt then clearing the interrupt status bit, wherein the throttling is suspended but still enabled, and clearing the interrupt status bit, disabling an existing throttling mode, handling the interrupt, then setting thermal management control registers back to an original value;
• and responsive to a determination to not clear the interrupt status bit at the beginning of the interrupt handler routine, disabling the existing throttling mode, handling the interrupt, and clearing the interrupt status bit at an end of the interrupt handler routine, wherein the thermal management control registers are set back to the original value.

A processor, comprising:

• at least one processing core;
• and
• a thermal management control state machine, wherein the processor executes a set of instructions to monitor, using the thermal management control state machine, a setting of an interrupt status bit in a thermal sensor interrupt status register;
• set the interrupt status bit when a temperature value in a thermal sensor current temperature status register for a sensor is greater than or equal to one of a corresponding sensor interrupt temperature value in a thermal sensor interrupt temperature register and a global interrupt temperature value in a thermal sensor global interrupt temperature register;
• determine whether to clear the interrupt status bit at a beginning of an interrupt handler routine:
• responsive to a determination to clear the interrupt status bit at a beginning of the interrupt handler routine, select one of handling the interrupt then clearing the interrupt status bit, wherein the throttling is suspended but still enabled, and clear the interrupt status bit, disable an existing throttling mode, handle the interrupt, then set thermal management control registers back to an original value;
• and responsive to a determination to not clear the interrupt status bit at the beginning of the interrupt handler routine, disable the existing throttling mode, handle the interrupt, and clear the interrupt status bit at an end of the interrupt handler routine, wherein the thermal management control registers are set back to the original value.