Efficient interrupt return address save mechanism
AssigneeQUALCOMM Incorporated
InventorsThomas Andrew Sartorius, Rodney Wayne Smith, Michael Scott McIlvaine
Life of this patent
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Abstract
A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.
Claims22
A data processing system comprising:
- a pipelined processor, the pipelined processor including:
- a general purpose register file;
- and
- control logic configured to generate a pseudo-instruction in response to an interrupt request, wherein the pseudo-instruction is configured to cause an interrupt return address to be written to the general purpose register file, the interrupt return address associated with a forwardmost instruction in a pipeline;
- wherein the pseudo-instruction is further configured to be inserted into a pipeline of the pipelined processor and travel down the pipeline in a substantially similar manner to other instructions that are inserted into the pipeline;
- wherein the pipeline comprises a plurality of stages including:
- a decode stage, wherein the decode stage is configured to decode the pseudo-instruction;
- and
- a write back stage, wherein the write back stage is configured to write results associated with the pseudo-instruction to the general purpose register file, the results including the interrupt return address associated with the forwardmost instruction.
An apparatus comprising:
- a pipelined processor including:
- a pseudo-instruction generator configured to generate a pseudo-instruction in response to an interrupt request, wherein the pseudo-instruction is configured to cause an interrupt return address associated with a forwardmost instruction in a pipeline of the pipelined processor to be written to a general purpose register file of the pipelined processor;
- wherein the pipeline comprises:
- a decode stage configured to decode the pseudo-instruction;
- and
- a write back stage, the write back stage configured to write results associated with the pseudo-instruction to the general purpose register file, the results including an interrupt return address associated with an incompletely processed instruction.
A method of saving an interrupt return address to a general purpose register file of a pipelined processor, the method comprising:
- in response to an interrupt request, generating a pseudo-instruction configured to cause an interrupt return address associated with a forwardmost instruction in a pipeline of the pipelined processor to be written to the general purpose register file of the pipelined processor;
- wherein the pipeline of the pipelined processor comprises:
- a decode stage and a write back stage, wherein the decode stage is configured to decode the pseudo-instruction, and wherein the write back stage is configured to write results associated with the pseudo-instruction to the general purpose register file, the results including the interrupt return address.
An apparatus comprising:
- a processor configured to perform interrupt processing, the processor including a pipeline, wherein the pipeline includes:
- a first stage configured to receive instructions;
- and
- a second stage configured to write back results to a general purpose register file;
- wherein the processor is further configured to process instruction data from a program;
- control logic configured to:
- generate a pseudo-instruction in response to an interrupt request, wherein the pseudo-instruction is configured to cause an interrupt return address associated with a forwardmost instruction in the pipeline to be written to a general purpose register file;
- wherein the pipeline further includes:
- a decode stage and a write back stage, wherein the decode stage is configured to decode the pseudo-instruction, and wherein the write back stage is configured to write results associated with the pseudo-instruction to the general purpose register file, the results including the interrupt return address;
- and
- a multiplexer configured to:
- receive the pseudo-instruction from the control logic and the instruction data from the program;
- and
- input the pseudo-instruction or the instruction data into the first stage;
- wherein, after interrupt processing, the processor is further configured to resume processing of the instruction data at the interrupt return address.
Dependencies are inferred from the claim text.