Pseudo pipeline and pseudo pipelined SDRAM controller

A method of controlling data flow comprising:

• generating at least one write pointer and a plurality of read pointers;
• writing data into one of a plurality of registers based upon said write pointer;
• and
• accessing read data from said plurality of registers in response to said plurality of read pointers, wherein the read data is presented as outputs of a plurality of pseudo pipeline stages and said plurality of read pointers are generated to provide pseudo pipelined operation, wherein
• (a) each of said plurality of read pointers is generated such that (i) said read data moves between the outputs of the plurality of pseudo pipeline stages and (ii) said read data remains in the register in which said read data was written rather than being moved between said plurality of registers, and
• (b) said pseudo pipelined operation comprises one or more of a plurality of modes including (i) a first mode characterized by a positive delay between adjacent pseudo pipeline stages, (ii) a second mode characterized by a negative delay between adjacent pseudo pipeline stages, (iii) a third mode characterized by one or more pseudo pipeline stages being skipped in a forward direction, (iv) a fourth mode characterized by one or more pseudo pipeline stages being skipped in a backwards direction, and (v) a fifth mode characterized by two or more pseudo pipeline stages presenting the same data simultaneously.

A memory controller comprising:

• a register file having at least one write port and a plurality of read ports, wherein said plurality of read ports are configured as outputs of a plurality of pseudo pipeline stages;
• and
• a control circuit configured to control the register file, wherein the plurality of pseudo pipeline stages provide pseudo pipelined operation and are configured as a precharge stage, a row access stage, a column access and write data stage, and a read data stage, and wherein
• (a) the register file comprises a plurality of registers,
• (b) data presented to the at least one write port is written to one of said plurality of registers based on a write address presented to said at least one write port,
• (c) each of the outputs of the plurality of pseudo pipeline stages is coupled to an output of one of said plurality of registers based on a respective read address presented to a respective one of the plurality of read ports,
• (d) each of the respective read addresses is generated such that (i) said data moves between the outputs of the plurality of pseudo pipeline stages and (ii) said data remains in the register in which said data was written rather than being moved between said plurality of registers, and
• (e) said pseudo pipelined operation comprises one or more of a plurality of modes including (i) a first mode characterized by a positive delay between adjacent pseudo pipeline stages, (ii) a second mode characterized by a negative delay between adjacent pseudo pipeline stages, (iii) a third mode characterized by one or more pseudo pipeline stages being skipped in a forward direction, (iv) a fourth mode characterized by one or more pseudo pipeline stages being skipped in a backwards direction, and (v) a fifth mode characterized by two or more pseudo pipeline stages presenting the same data simultaneously.