Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation

A method of accessing a memory, comprising:

• receiving an external row address;
• selecting a burst mode of operation or a pipeline mode of operation of the memory;
• selecting a read operation or a write operation for the memory;
• selecting an external address only data path, obtaining an external column address, and obtaining information from the memory if the read operation of the pipeline mode of operation is selected;
• selecting an external address only data path, obtaining an external column address, and providing information to the memory if the write operation of the pipeline mode of operation is selected;
• selecting an initial buffered external address data path, obtaining an initial external column address, obtaining information from the memory, and generating internal column addresses and obtaining further information from the memory until all desired internal column addresses are used if the read operation of the burst mode of operation is selected;
• and
• selecting an initial buffered external address data path, obtaining an initial external column address, providing information to the memory, and generating internal column addresses and providing further information to the memory until all desired internal column addresses are used if the write operation of the burst mode of operation is selected.

A method of operating a memory circuit, comprising:

• receiving a mode select signal;
• receiving an initial external address;
• selecting a read or a write operation of the memory;
• cycling a second enabling signal multiply between active and inactive;
• generating an internal address on a cycle of the second enabling signal based on the initial external address;
• changing the mode select signal to select a pipeline mode of operation while maintaining a first enabling signal in an active state;
• and
• receiving an external address on each cycle of the second enabling signal.

A method for accessing a memory, comprising:

• maintaining a first enabling signal in an active state;
• maintaining a mode select signal to select a burst mode of operation;
• receiving an initial external address;
• selecting a read or a write operation of the memory;
• cycling a second enabling signal multiply between inactive and active;
• generating an internal address on a cycle of the second enabling signal based on the initial external address;
• and
• switching the mode of operation to a pipeline mode on successive cycles of the second enabling signal by changing the mode select signal.

A method for operating a memory, comprising:

• maintaining a first enabling signal in an active state;
• maintaining a mode select signal to select a burst mode of operation;
• selecting a read operation or a write operation of the memory;
• receiving a stream of addresses and cycling a second enabling signal for processing the stream of addresses;
• and
• changing the mode select signal to select a pipeline mode of operation.

A method for accessing an asynchronously-accessible dynamic random access memory (DRAM), comprising:

• receiving an external row address to the asynchronously-accessible DRAM;
• switching from a burst mode of operation to a pipelined mode of operation;
• selecting a memory operation selected from a group consisting of a read operation and a write operation;
• and
• obtaining a first external colunm address for accessing the asynchronously-accessible DRAM.

A method for accessing an asynchronously-accessible dynamic random access memory (DRAM), comprising:

• receiving an external row address to the asynchronously-accessible DRAM;
• switching from a burst mode of operation to a pipelined mode of operation;
• selecting a memory read operation;
• and
• obtaining a first external column address for accessing the asynchronously-accessible DRAM.