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US 7,680,988 B1Granted
Single interconnect providing read and write access to a memory shared by concurrent threads
AssigneeNVIDIA Corporation
InventorsJohn R. Nickolls, Brett W. Coon, Ming Y. Siu, Stuart F. Oberman, Samuel Liu
Life of this patent
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Abstract
A shared memory is usable by concurrent threads in a multithreaded processor, with any addressable storage location in the shared memory being readable and writeable by any of the threads. Processing engines that execute the threads are coupled to the shared memory via an interconnect that transfers data in only one direction (e.g., from the shared memory to the processing engines); the same interconnect supports both read and write operations. The interconnect advantageously supports multiple parallel read or write operations.
Claims21
A processor core comprising:
- a shared memory having a plurality of addressable storage locations;
- a plurality of processing engines each adapted to execute a different thread of a group of threads in parallel, each thread of the group of threads including at least one instruction that, when executed, results in an access to a target one of the addressable storage locations in the shared memory;
- and
- an interconnect circuit coupling the plurality of processing engines to the shared memory such that any one of the addressable storage locations in the shared memory is readable and writeable by any one of the processing engines, wherein the interconnect circuit is adapted such that first data read from the shared memory by a selected one of the processing engines and second data written to the shared memory by the selected one of the processing engines is transferred through at least a portion of the interconnect circuit in a same direction during both read operations and write operations.
1 more element
A method of writing data to a shared memory in a processor having an array of parallel processing engines, the method comprising:
- identifying a write-source location for write data, the write-source location being a local storage location associated with a source processing engine of the array of parallel processing engines;
- identifying a write-target location in the shared memory to which the write data is to be written, the write-target location being writeable via a direct path by a surrogate processing engine of the array of parallel processing engines;
- transferring the write data from the write-source location to the surrogate processing engine via an interconnect circuit adapted to selectably deliver data from any location in the shared memory or any local storage location to any one of the processing engines, wherein the interconnect circuit is adapted such that the write data to be written to the shared memory by the surrogate processing engine and read data read from the shared memory by a destination processing engine of the array of processing engines are transferred through at least a portion of the interconnect circuit in a same direction during both read operations and write operations;
- and
- operating the surrogate processing engine to write the write data via the direct path to the write-target location in the shared memory.
2 more elements
A method of writing data to a shared memory in a processor having an array of parallel processing engines, the method comprising:
- identifying, in parallel, a first source location for first data to be written and a second source location for second data to be written, the first source location and the second source location being associated, respectively, with a first source processing engine of the array of parallel processing engines and a second source processing engine of the array of parallel processing engines;
- identifying, in parallel, a first target location for the first data and a second target location for the second data, each of the first and second target locations being in the shared memory, wherein the first target location is writeable via a direct path by a first surrogate processing engine of the array of parallel processing engines and the second target location is writeable via a direct path by a second surrogate processing engine of the array of parallel processing engines;
- transferring, in parallel, the first data and the second data from the first and second source locations to the first and second surrogate processing engines, respectively, via an interconnect circuit adapted to deliver data from any location in the shared memory to any one of the processing engines, wherein the interconnect circuit is adapted such that the first data and the second data to be written to the shared memory by the first and second surrogate processing engines, and third data read from the shared memory by a destination processing engine of the array of processing engines, are transferred through at least a portion of the interconnect circuit in a same direction during both read operations and write operations;
- and
- operating, in parallel, the first and second surrogate processing engines to write the first data and the second data to the first target location and the second target location, respectively.
2 more elements
Dependencies are inferred from the claim text.