Method and apparatus for accessing a split cache directory

#This application is related to U.S. patent application Ser. No. 11/769,978, entitled L2 CACHE/NEST ADDRESS TRANSLATION, filed Jun. 28, 2007, by David Arnold Luick; and U.S. patent application Ser. No. 11/770,036, entitled METHOD AND APPARATUS FOR ACCESSING A CACHE WITH AN EFFECTIVE ADDRESS, filed Jun. 28, 2007, by David Arnold Luick. These related patent applications are herein incorporated by reference in its entirety.

#1. Field of the Invention

#The present invention generally relates to executing instructions in a processor.

#So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.

#It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

#FIG. 1 is a block diagram depicting a system according to one embodiment of the invention.

#The present invention generally provides a method and apparatus for accessing a cache. The method includes receiving a request to access the cache. The request includes an address of requested data to be accessed. The method also includes using a first portion of the address to perform an access to a first directory for the cache and using a second portion of the address to perform an access to a second directory for the cache. Results from the access to the first directory for the cache and results from the access to the second directory for the cache are used to determine whether the cache includes the requested data to be accessed. In some cases, by splitting access to the cache directory into accesses to the first directory and the second directory, an access to the cache may be performed more quickly, thereby improving performance of a processor when accessing the cache memory system.

#In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, in various embodiments the invention provides numerous advantages over the prior art. However, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).

#The following is a detailed description of embodiments of the invention depicted in the accompanying drawings. The embodiments are examples and are in such detail as to clearly communicate the invention. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.