Method and apparatus for granting processors access to a resource

A method for granting one or more requesting entities access to a resource in a predetermined time interval, said requesting entity asserting a request signal for accessing said resource, said method comprising:

• receiving, at a first circuit device, said asserted request signals and implementing logic in response to control signals received at said first circuit device at each successive predetermined time interval, for assigning a priority to said one or more request signals,
• generating a set of first_request signals based on said priorities assigned to said received request signals;
• receiving, at a priority select circuit, said set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during said predetermined time interval;
• receiving, at a second circuit device, said one or more fixed grant signals and implementing logic for generating one or more grant signals associated with one or more highest priority request signals assigned, said grant signals for enabling one or more respective requesting entities access to said resource in said predetermined time interval;
• and,
• changing, at said first circuit device, in response to received said control signals said assigned priority of each said request signals at each successive predetermined time interval.

In a multiprocessor computer system having a plurality of processor devices and associated memory storage devices, wherein each processor device broadcasts event request signals to other processor devices in the system for requesting said other processor devices to perform actions at respective said associated memory storage devices, a coherence logic device associated with each processor device for intercepting said broadcast event request signals from said other processors devices, said coherence logic device comprising:

• a plurality of queue structures adapted for receiving and enqueuing said intercepted event request signals associated with a respective requesting processor device;
• and,
• arbitration device for selecting, during an arbitration cycle, one or more queue structures for dequeuing available enqueued event request signals when available for input to said associated processor device according to an assigned priority, said arbitration device selecting up to two or more queue structures for dequening a respective enquened event request signal every arbitration cycle, and, said arbitration device comprises:
• a first circuit means for receiving one or more request signals and implementing logic in response to received control signals at each successive arbitration cycle for assigning a priority to said one or more request signals, said logic effecting a change of assigned priority for each request signal at each successive arbitration cycle, and, generating a set of first_request signals based on said priorities assigned to received request signals;
• one or more priority select circuits for receiving said set of first_request signals and generating corresponding one or more fixed grant signals representing one or more highest priority request signals when asserted during said arbitration cycle;
• second circuit means receiving said one or more fixed grant signals and implementing logic for generating one or more grant signals associated with one or more highest priority request signals assigned, said grant signals for enabling one or more respective requesting entities access to said resource in said arbitration cycle.