Memory interface including generation of timing signals for memory operation
AssigneeNational Semiconductor Corporation
InventorsOhad Falik, Paul Johnston
Life of this patent
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Abstract
A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any within a given range of frequencies. A frequency value signal conveying the value of the frequency of the clock signal is also transmitted. The interface controller includes circuitry for deriving from the clock signal and from the frequency value signal at least one timing signal for any operation in the memory device.
Claims23
A memory device, comprising:
- at least one memory;
- and
- an interface controller capable of receiving:
- a clock signal;
- and
- a frequency value identifying a frequency of the clock signal;
- wherein the interface controller comprises:
- a timing generator using the clock signal and the frequency value to provide access to the at least one memory;
- an address buffer storing an address associated with the at least one memory;
- and
- circuitry coordinating the address in the address buffer with an address in an address buffer of a semiconductor device, the semiconductor device providing the clock signal to the interface controller, the address buffer in the semiconductor device also storing the address associated with the at least one memory, wherein the addresses in the address buffer of the semiconductor device and the addresses in the address buffer have an overlapping address space.
An interface controller, comprising:
- a timing generator capable of receiving a clock signal and a frequency value identifying a frequency of the clock signal, the timing generator further capable of using the clock signal and the frequency value to generate at least one signal;
- a memory controller capable of using the at least one signal to provide access to at least one memory;
- an address buffer capable of storing an address associated with the at least one memory;
- and
- circuitry capable of coordinating the address in the address buffer with an address in an address buffer of a semiconductor device, the semiconductor device capable of providing the clock signal to the interface controller, the address buffer in the semiconductor device also capable of storing the address associated with the at least one memory.
A method, comprising:
- receiving a clock signal at a memory device;
- receiving a frequency value identifying a frequency of the clock signal;
- using the frequency value to identify a needed number of clock cycles to read data from at least one memory during a read operation;
- using the clock signal and the frequency value to provide access to the at least one memory;
- storing an address associated with the at least one memory in an address buffer;
- reading the data from the at least one memory after the needed number of clock cycles are received on the clock signal;
- and
- coordinating the address in the address buffer with an address in an address buffer of a semiconductor device, the semiconductor device providing the clock signal to the memory device, the address buffer in the semiconductor device also storing the address associated with the at least one memory.
Dependencies are inferred from the claim text.