DMA controller configured to process control descriptors and transfer descriptors

An apparatus comprising:

• a host comprising a memory system configured to store one or more descriptor data structures, the descriptor data structures storing Direct Memory Access (DMA) descriptors describing DMA transfers;
• and
• a Direct Memory Access (DMA) controller coupled to the host, the DMA controller comprising one or more configuration registers programmable to control the DMA controller, wherein the DMA controller is configured to perform the DMA transfers described in the DMA descriptors, and wherein, in response to a control descriptor included in the descriptor data structures, the DMA controller is configured to write one or more of the configuration registers to reconfigure the DMA controller, wherein the control descriptor comprises a header and a data portion, and wherein the data portion comprises a pointer to the memory, wherein the memory at the location pointed to by the pointer comprises a list of register addresses of the configuration registers to be written and the data to be written to the configuration registers.

An apparatus comprising:

• a host comprising a memory system configured to store one or more descriptor data structures, the descriptor data structures storing Direct Memory Access (DMA) descriptors describing DMA transfers;
• and
• a Direct Memory Access (DMA) controller coupled to the host, the DMA controller comprising one or more configuration registers programmable to control the DMA controller, wherein the DMA controller is configured to perform the DMA transfers described in the DMA descriptors, and wherein, in response to a control descriptor included in the descriptor data structures, the DMA controller is configured to write one or more of the configuration registers to reconfigure the DMA controller, and wherein the control descriptor comprises a header and a data portion, and wherein the data portion comprises a pointer to the memory, wherein the memory at the location pointed to by the pointer comprises a list of data to be written to configuration registers, and wherein an address of an initial register is stored in the data portion.

An apparatus comprising:

• a host comprising a memory system configured to store one or more descriptor data structures, the descriptor data structures storing Direct Memory Access (DMA) descriptors describing DMA transfers;
• and
• a Direct Memory Access (DMA) controller coupled to the host, the DMA controller comprising one or more configuration registers programmable to control the DMA controller, wherein the DMA controller is configured to perform the DMA transfers described in the DMA descriptors, and wherein, in response to a control descriptor included in the descriptor data structures, the DMA controller is configured to write one or more of the configuration registers to reconfigure the DMA controller, and wherein, in response to a second control descriptor included in the descriptor data structure, the DMA controller is configured to read one or more configuration registers.

A method comprising:

• a direct memory access (DMA) controller performing a first DMA transfer responsive to a first transfer descriptor in a first descriptor data structure stored in a memory system of a host to which the DMA controller is coupled, wherein the DMA controller comprises one or more configuration registers programmable to control the DMA controller;
• and
• the DMA controller writing one or more of the configuration registers to reconfigure the DMA controller in response to a control descriptor included in the descriptor data structures, wherein the control descriptor describes the write of the one or more configuration registers and does not describe a DMA transfer.

A direct memory access (DMA) controller comprising:

• one or more configuration registers programmable to control the DMA controller;
• and
• circuitry coupled to the one or more configuration registers and configured to write at least some of the one or more of the configuration registers to reconfigure the DMA controller in response to a control descriptor included in a descriptor data structure stored in a memory system of a host to which the DMA controller is coupled during use, wherein the descriptor data structure further stores transfer descriptors that describe DMA transfers, and wherein the control descriptor does not describe a DMA transfer.