Method for configuration of a processing unit
AssigneeIttiam Systems (P) Ltd.
InventorsShantanu Prasad Prabhudesai, Satheesh Sadanand
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AssigneeIttiam Systems (P) Ltd.
InventorsShantanu Prasad Prabhudesai, Satheesh Sadanand
Estimating the term…
A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system is presented. The multiprocessor system has at least a Main Processing Unit (MPU) coupled to the APU via a communication link. The APU has at least a first memory and a second memory. The method includes a plurality of steps. At step the first memory is divided into an application sector, a boot sector and a common sector. At another step interrupts of the APU except interrupt/s that is/are being received via the communication link are disabled. At a further step interrupt vector/s pertaining to the communication link is/are mapped to the boot sector of the first memory. At another step a configuration code is received selectively into the application sector of the first memory and into the second memory. At a further step the interrupt/s that is/are being received via the communication link are disabled. At a further step the common sector of the first memory is updated from the second memory.
A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system, the multiprocessor system having at least a Main Processing Unit (MPU) coupled to the APU via a communication link, the APU has at least a first memory and a second memory, the method comprising steps of:
Dependencies are inferred from the claim text.
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Digital computers in general ; Data processing equipment in general: combinations of two or more digital computers each having at least an…
Computing and data processing
About 1 year 2 months of term left · ends 31 Dec 2027 (estimated)
The invention relates to a method of configuration of a processing unit, more specifically the invention relates to a method for configuration of a processing unit in a multiprocessor system.
A multiprocessor system (hereinafter “system”) includes a number of processing units. For configuring these units, a communication link, with each unit, capable of interacting with resources external to the multiprocessor system is required. Often extra real estate on silicon is required to provide these communication links. In many cases, not all the processing units of the system are required to interact with the resources external to the system. In such cases, the sole purpose of the communication link remains limited to configuration of the processing unit. Providing for a communication link on the silicon for a single purpose is not only area inefficient but also, expensive affair.
Moreover, upgradation of these systems may involve updating of on board memory where the non-volatile code resides. This updating of on board memory may result in loss and/or alteration of data that may be required by the processing unit which is being upgraded.
Example embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
FIG. 1 is an example multiprocessor system;
FIG. 2 is a flow diagram of an embodiment of a method in accordance with the present subject matter;
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.
In the following detailed description of the various embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
A system and method for configuration of an Auxiliary Processing Unit (APU) in a multi-processor system is disclosed. The multiprocessor system includes a Main Processing Unit (MPU) coupled to the APU using a communication link. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It will be evident, however to one skilled in the art that other embodiments may be practiced without departing from the scope of the subject matter.