Canonical signed digit (CSD) coefficient multiplier with optimization
AssigneeVIA Telecom Co., Ltd.
InventorAlon Saado
Life of this patent
Estimating the term…
Abstract
An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.
Claims20
An apparatus comprising:
- an address generation circuit configured to generate a series of addresses;
- a lookup table configured to generate one or more coefficients in response to said addresses, each one of said coefficients having a plurality of bits;
- a multiplexer circuit configured to generate one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits;
- and
- an output circuit configured to (i) generate one or more component values by rounding said shifted values, (ii) negate selective ones of said component values and (iii) generate an output signal by combining said component values after said negating, wherein (a) said component values are grouped as one over power of 2 components into mutually exclusive groups, (b) each one of said groups corresponds to a respective one of said bits and (c) said output signal is suitable for use in a digital filter.
An apparatus comprising:
- means for generating a series of addresses;
- means for generating one or more coefficients in response to said addresses, each one of said coefficients having a plurality of bits;
- means for generating one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits;
- and
- means for (i) generating one or more component values by rounding said shifted values, (ii) negating selective ones of said component values, and (iii) generating an output signal by combining said component values after said negating, wherein (a) said component values are grouped as one over power of 2 components into mutually exclusive groups, (b) each one of said groups corresponds to a respective one of said bits and (c) said output signal is suitable for use in a digital filter.
A method for implementing a multiplier comprising the steps of:
- (A) generating a series of addresses;
- (B) generating one or more coefficients from a lookup table in response to said addresses, each one of said coefficients having a plurality of bits;
- (C) generating one or more shifted values by multiplexing one or more operands and a plurality of arithmetically shifted versions of said operands, wherein said multiplexing is controlled by said coefficients such that each of said shifted values represents one of (i) said operands or (ii) said arithmetically shifted versions of said operands multiplied by a corresponding one of said bits;
- (D) generating one or more component values by rounding said shifted values;
- (E) negating selective ones of said component values;
- and
- (F) generating an output signal by combining said component values after said negating, wherein (i) said component values are grouped as one over power of 2 components into mutually exclusive groups, (ii) each one of said groups corresponds to a respective one of said bits and (iii) said output signal is suitable for use in a digital filter.
Dependencies are inferred from the claim text.