System and method of analyzing timing effects of spatial distribution in circuits

A method for analyzing the timing of a circuit, comprising:

• determining at least one location information for one or more inputs to a timing test;
• computing a timing slack for the timing test using the at least one location information;
• and
• one of:
• designing the circuit based on the analysis of the timing;
• and
• identifying the cause of timing failures in an existing circuit,
• wherein the at least one location information comprises a centroid of the one or more inputs to the timing test, and
• wherein the at least one location information refers to a physical location of a particular element in a circuit layout relative to a coordinate system.

A computer-readable medium containing instructions that, when executed, cause a computer to:

• determine at least one location information for one or more inputs to a timing test;
• compute a timing slack variation for the timing test using the at least one location information;
• and
• one of:
• design a circuit;
• and
• identify the cause of timing failures in an existing circuit,
• wherein the one or more inputs comprise cells or elements of interest,
• wherein the at least one location information refers to a physical location of a particular element in a circuit layout relative to another element in the circuit layout, and
• wherein the method predicts a delay in circuit paths by considering a portion of the delay that is influenced by a proximity of circuit elements in a path or paths separately from a full delay distribution.

A computer-readable medium containing instructions that, when executed, cause a computer to:

• determine at least one location information for one or more inputs to a timing test;
• compute a timing slack for the timing test using the at least one location information;
• and
• one of:
• design a circuit;
• and
• identify the cause of timing failures in an existing circuit,
• wherein the at least one location information comprises a centroid of the one or more inputs to the timing test, and
• wherein the at least one location information refers to a physical location of a particular element in a circuit layout relative to a coordinate system.

A method of analyzing the timing of an integrated circuit, comprising:

• identifying an early path and a late path in the integrated circuit;
• determining a timing slack variation in the early path using location information on one or more elements in the early path;
• determining a timing slack variation in the late path using location information on one or more elements in the late path;
• computing a new timing slack for the early path and the late path by using the timing slack variation in the early path and the timing slack variation in the late path;
• and
• one of:
• designing the integrated circuit based on the analysis of the timing;
• and
• identifying the cause of timing failures in an existing circuit,
• wherein the location information refers to physical location of a particular element in a circuit layout relative to another element in the circuit layout or relative to a coordinate system.