Method and system to compensate for lamp intensity differences in a photolithographic inspection tool
AssigneeTokyo Electron Limited
InventorsDavid Dixon, Lloyd Lee
Life of this patent
Estimating the term…
Loading patent…
AssigneeTokyo Electron Limited
InventorsDavid Dixon, Lloyd Lee
Estimating the term…
An after develop inspection tool considers tool-to-tool variability when determining confidence score for wafers under inspection. A golden wafer is used to calculate a RGB signature as well as the slope of the individual RGB curves for different lamp intensities. These slopes are normalized in order to generate a compensation factor for red values and blue values within a signature. When a wafer is subsequently inspected at an ADI station using a different lamp, the test wafer RGB signature is likely captured at a different lamp intensity. Consequently, when comparing the signatures, the golden wafer RGB signature is adjusted by the compensation factors, based on the different lamp's intensity setting, and this adjusted RGB signature is then used to determine whether a defect exists on the test wafer.
An after develop inspection system, comprising:
An after develop inspection system, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Inspecting patterns on the surface of objects: using a comparative method
Calibration, base line adjustment, drift correction: constitution of standards
Investigating the presence of flaws or contamination: detection standards; Calibrating baseline adjustment, drift correction
Characterised by the material or shape of the object to be examined: semiconductor wafers
Term ended 31 Dec 2023 (estimated)
The following invention relates to inspection equipment in photolithographic environments and, more particularly, to automated control of such equipment.
The lithography process for fabricating semiconductor devices can be broken down into three general steps: coating; align/expose, develop. After the develop step is completed, the wafer is inspected for defects which may have occurred in any of the three lithography process areas. Typical defects include problems with photo resist or ARC/BARC coating, edge bead processing, exposure, alignment, development, as well as defects caused by contamination or handling, such as particles or scratches.
Although the chance of misprocessing at any single lithography step is small, a typical wafer goes through 20 to 25 lithography steps. Excursions due to process equipment problems, mishandling, and contamination can occur at each of these steps, so the cumulative probability of a wafer experiencing a yield-limiting defect becomes significant. While most defects impact only a small area of the wafer and do not require rework, some defects impact 30% or more of the wafer. These are defined as global defects. After develop inspection (ADI) procedures detect, classify, and disposition wafers with global lithography defects for rework. Each recovered wafer can result in savings of thousands, or even tens of thousands of dollars, in revenue.
FIG. 1 is a schematic illustration of a photolithographic fabrication environment in which embodiments of the present invention have applicability.
FIGS. 2A-2D are a graphical representation illustrating the effect varying lamp intensity has on the values on a RGB signature for four different tools.
FIG. 3 depicts a flowchart of an exemplary algorithm to account for tool-to-tool lamp variability in an after develop inspection tool according to embodiments of the present invention.
During the photo lithography process, a wafer can undergo a variety of coating, exposing and developing steps. Also, throughout the process, a number of different inspection tools can be used at various stages of fabrication to perform ADI or other types of inspection.
FIG. 1 depicts a schematic view of an automated photo lithography system. In this system, a central control system 102 coordinates the operation of the different processing stations 106, 110 and inspection tools 108, 112. Furthermore, the central control system 102 likely controls the automated transport of wafers between the different stations 106, 108, 110, 112, although such a mechanism is not explicitly depicted in FIG. 1.
The control system 102 can be a programmable computer, or other dedicated microcontroller in communication with each of the process stations 106, 110 and tools 108, 112. When fabricating a wafer, it will run a process recipe and an inspection recipe, each of which specifies the steps and their order necessary to complete the fabrication of the wafer. These recipes can be stored at a central storage 104 of the central control system 102 and can either be executed by the central control system 102 to control a station 106, 110 or tool 108, 112, or can be transmitted to the tool 106, 110 or station 108, 112 for remote execution. Furthermore, the recipes can be distributed to storage 120a-120d locally connected to one of the stations 106, 110 or tools 108, 112.