Hybrid analog/digital phase-lock loop for low-jitter synchronization

A method of providing a low-jitter clock signal synchronized to a timing reference having jitter, said method comprising:

• generating a clock output from a numerically-controlled analog oscillator ratiometrically locked to a stable clock source, wherein a frequency of said clock output is controlled by a rational numeric representation of a ratio between a frequency of said clock output and a frequency of said stable clock;
• dividing a frequency of one of said clock output and said stable clock;
• generating a representation of an on-going phase-frequency difference between said timing reference and a result of said dividing;
• and
• filtering said representation of said on-going phase-frequency difference with a digital filter to provide said rational numeric representation to said numerically-controlled analog oscillator.

A numerically-controlled analog oscillator circuit integrated on a single die, comprising:

• a voltage controlled oscillator for providing a clock output;
• an inductor-capacitor resonator tuned (LC) oscillator for providing a stable clock;
• a local divider for dividing said clock output in conformity with a divisor input;
• a phase-frequency detector for comparing an output of said local divider with said stable clock;
• an analog loop filter for filtering an output of said phase-frequency detector to provide a control input of said voltage controlled oscillator;
• and
• a delta-sigma modulator having an input coupled to an output of said phase-frequency detector and an output providing said divisor input of said local divider.