Method and apparatus for signal phase locking
AssigneeSchneider Electric USA, Inc.
InventorsRoy Stephen Colby, Mark John Kocher, Gerald Benjamin Carson
Life of this patent
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Abstract
A phase locked loop (PLL) circuit provides ac devices, such as power inverters and power measurement devices, with a reliable means for synchronizing to ac electrical systems. In an exemplary embodiment, the PLL circuit is configured for operation with single-phase electrical systems and offers substantial noise immunity by basing its locking operations on measured fundamental components, i.e., measured x-y phasors, of the electrical system voltage. Further, with its phasor-based locking operations and with its timer/counter-based operation, the PLL circuit can be implemented partly or wholly in digital processing logic.
Claims22
A computer readable medium storing a computer program to implement a Phase-Locked Loop (PLL), the computer program comprising:
- program instructions to generate a product signal by multiplying an input signal of interest representing an in-phase fundamental component of an ac voltage waveform with a PLL output signal to be locked with the input signal;
- program instructions to generate a substantially dc phase error signal by averaging the product signal over half-cycles of a waveform period of interest;
- program instructions to generate a frequency correction signal based on proportional-integral processing of the substantially dc phase error signal;
- and
- program instructions to generate the PLL output signal by clocking through a waveform lookup table at a desired clock rate determined by configuring a digital counter to generate a periodic clock signal at a period determined by a configuration value, and to adjust that clock rate as a function of the substantially dc phase error signal by adjusting the period as a function of the frequency correction signal to output successive sine and cosine values from a stored data table.
A Phase-Locked Loop (PLL) circuit comprising:
- a phase detector circuit including a multiplier to generate a product signal by multiplying an input signal of interest with a PLL output signal to be locked with the input signal, and a normalizer circuit to normalize the product signal as a function of a magnitude of the input signal of interest, the normalizer circuit having a vector magnitude calculator to compute one or more fundamental components of the input signal of interest, and a scaler circuit to normalize the product signal using the one or more fundamental components of the input signal of interest, the phase detector circuit configured to generate a phase error signal by averaging the product signal over half-cycles of a waveform period of interest;
- a loop filter circuit to generate a frequency correction signal by filtering the phase error signal;
- and
- an oscillator circuit comprising a counter circuit configured to generate the PLL output signal by clocking through a waveform lookup table at a desired clock output signal rate, and wherein the counter circuit is configured to adjust that clock output signal rate as a function of the phase error signal.
A method of locking an output signal to a frequency and phase of an input signal of interest using a digital processor, the method comprising:
- generating a PLL output signal to be locked with a frequency and phase of a periodic input signal of interest, a digitized voltage waveform obtained from an ac voltage signal, by running a digital counter circuit at a known clock rate, setting a cycle count of the digital counter circuit to a nominal value corresponding to a nominal period;
- multiplying the input signal of interest by die PLL output signal to generate a product signal and filtering the product signal over a desired number of half-cycles to generate a substantially dc phase error term;
- calculating a frequency correction signal, as a delta count value, from the substantially dc phase error term, and increasing or decreasing the cycle count by applying the delta count value to the cycle count such that the nominal period is adjusted as a function of the frequency correction signal;
- outputting table lookup values corresponding to a desired output waveform at a rate determined as a function of the frequency correction signal;
- and
- adjusting a frequency of the PLL output signal responsive to the frequency correction signal to lock the output signal to the input signal.
Dependencies are inferred from the claim text.