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US 7,680,232 B2Granted
Method and apparatus for multi-mode clock data recovery
AssigneeAltera Corporation
InventorsSergey Y Shumarayev, Rakesh H Patel, Wilson Wong, Tim T Hoang
Life of this patent
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Abstract
The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value.
Claims20
A multi-mode clock data recovery circuit having at least two modes of operation, comprising:
- a switch that conveys a recovered clock signal to a frequency detector and a phase detector;
- a first mode of operation in which the switch is coupled to an output of a controlled oscillator, the switch conveying said output of said controlled oscillator as the recovered clock signal;
- and
- a second mode of operation in which the switch is coupled to an output of a phase interpolator, the switch conveying said output of said phase interpolator as the recovered clock signal,
- wherein in the first mode of operation, if a frequency of the recovered clock signal differs from a frequency of a reference clock signal by at least a tolerance point, an output of the frequency detector is selectively conveyed to the controlled oscillator at least until the frequency of the recovered clock signal differs from the frequency of the reference clock signal by at most an acceptable difference.
2 more elements
A multi-mode clock data recovery circuit having at least two modes of operation, comprising:
- a first connection to receive a recovered clock signal;
- a second connection capable of providing a data signal;
- a reference clock source that provides a reference clock signal;
- a phase detector coupled to the first connection and the second connection and having a phase detector output connection;
- a frequency detector coupled to the first connection and the reference clock source and having a frequency detector output connection;
- and
- a switch that has a non-coupling position and at least two positions for conveying signals to a controlled oscillator, the at least two positions comprising:
- a first position in which the switch couples to said phase detector output connection, and
- a second position in which the switch couples to said frequency detector output connection,
- wherein:
- in a first mode of operation, the switch is selectively operated between the at least three positions, and if a frequency of the recovered clock signal differs from a frequency of the reference clock signal by at least a tolerance point, the switch is operated in the second position at least until the frequency of the recovered clock signal differs from the frequency of the recovered clock signal by at most an acceptable difference, and
- in a second mode of operation, the switch is operated to he in the second position.
9 more elements
A multi-mode clock data recovery circuit having at least two modes of operation, comprising:
- a first connection to receive a recovered clock signal;
- a second connection capable of providing a data signal;
- a reference clock source that provides a reference clock signal;
- a phase detector coupled to the first connection and the second connection and having a phase detector output connection;
- a frequency detector coupled to the first connection and the reference clock source and having a frequency detector output connection;
- and
- a switch that has a non-coupling position and at least two positions for conveying signals to a controlled oscillator, the at least two positions comprising:
- a first position in which the switch couples to said phase detector output connection, and
- a second position in which the switch couples to said frequency detector output connection,
- wherein:
- in a first mode of operation, the switch is selectively operated between the at least three positions, and if the second connection contains a data signal, the switch is operated in the first position, and
- in a second mode of operation, the switch is operated to be in the second position.
9 more elements
A multi-mode clock data recovery circuit having at least two modes of operation, comprising:
- a first connection to receive a recovered clock signal;
- a second connection capable of providing a data signal;
- a reference clock source that provides a reference clock signal;
- a phase detector coupled to the first connection and the second connection and having a phase detector output connection;
- a frequency detector coupled to the first connection and the reference clock source and having a frequency detector output connection;
- and
- a switch that has a non-coupling position and at least two positions for conveying signals to a controlled oscillator, the at least two positions comprising:
- a first position in which the switch couples to said phase detector output connection, and
- a second position in which the switch couples to said frequency detector output connection,
- wherein:
- in a first mode of operation, the switch is selectively operated between the at least three positions, and if the second connection contains a data signal and if a frequency of the recovered clock signal differs from a frequency of the reference clock signal by at least a tolerance point, the switch is operated in the second position, and
- in a second mode of operation the switch is operated to be in the second position.
9 more elements
A multi-mode clock data recovery circuit having at least two modes of operation, comprising:
- a first connection to receive a recovered clock signal;
- a second connection capable of providing a data signal;
- a reference clock source that provides a reference clock signal;
- a phase detector coupled to the first connection and the second connection and having a phase detector output connection;
- a frequency detector coupled to the first connection and the reference clock source and having a frequency detector output connection;
- and
- a switch that has a non-coupling position and at least two positions for conveying signals to a controlled oscillator, the at least two positions comprising:
- a first position in which the switch couples to said phase detector output connection, and
- a second position in which the switch couples to said phase detector output connection,
- wherein:
- in a first mode of operation, the switch is selectively operated between the at least three positions, and if the second connection does not contain data signal and if a frequency of the recovered clock signal differs from a frequency of the reference clock signal by less than a tolerance point, the switch is operated in the non-coupling position, and
- in a second mode of operation,, the switch is operated to be in the second position.
9 more elements
A method of generating a recovered clock signal for an application having a transmission frequency F and a consecutive identical digits requirement CID, the method comprising:
- providing a multi-mode clock data recovery circuit having at least a phase detector, a frequency detector, a controlled oscillator, and a phase interpolator;
- operating the multi-mode clock data recovery circuit in a first mode if the quantity (CID/F) is less than a threshold time;
- and
- operating the multi-mode clock data recovery circuit in a second mode if the quantity (CID/F) is greater than the threshold time.
1 more element
A multi-mode clock data recovery circuit with at least two modes of operation, comprising:
- a voltage controlled oscillator that produces a first recovered clock signal and phase shifted versions of the first recovered clock signal;
- a phase interpolator that is coupled to receive the first recovered clock signal and the phase shifted versions of the first recovered clock signal and that produces a second recovered clock signal based on the first recovered clock signal and the phase shifted versions of the first recovered clock signal;
- and
- a feedback path, wherein the feedback path is coupled to receive one of the first recovered clock signal and the phase shifted versions of the first recovered clock signal when the multi-mode clock data recovery circuit is operated in a first mode of operation and wherein the feedback path is coupled to receive the second recovered clock signal when the multi-mode clock data recovery circuit is operated in a second mode of operation,
- wherein in the first mode of operation, if a frequency of the first recovered clock signal differs from a frequency of a reference clock signal by at least a tolerance point, an output of a frequency detector is selectively conveyed to the voltage controlled oscillator at least until the frequency of the first recovered clock signal differs from the frequency of the reference clock signal by at most an acceptable difference.
2 more elements
Dependencies are inferred from the claim text.