US 7,680,231 B2 · Adaptive variable length pulse synchronizer

Abstract

An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided. In one embodiment, the synchronous pulse occurs between successive rising edges of the clock whereas the synchronous ready signal is provided in response to the intermediate falling edge of the clock.

Claims18

Dependent claims

An adaptive variable length pulse synchronizer which detects an asynchronous pulse in response to a request signal and which captures corresponding asynchronous data, said adaptive variable length pulse synchronizer comprising:

a state keeper circuit which transitions a first signal to a first logic state upon detection of a leading edge of the asynchronous pulse when the request signal is provided and which keeps said first signal in said first logic state while the request signal is provided;
an asynchronous pulse edge detection circuit which transitions a second signal to a second logic state in response to a trailing edge of the asynchronous pulse if said first signal is in said first logic state, and which provides a synchronous pulse synchronized with a clock signal when said second signal is in said second logic state;
a data synchronization circuit which latches the asynchronous data and provides said synchronous data in response to a leading edge of said synchronous pulse;
and
a pulse edge synchronization circuit which provides a synchronous ready signal after a leading edge of said synchronous pulse and before a trailing edge of said synchronous pulse.

2 more elements

An adaptive pulse synchronizer, comprising:

a first latch circuit having a data input receiving a fixed logic state, a clock input receiving an asynchronous pulse, a reset input receiving a request signal, and an output;
a second latch circuit having a data input coupled to said output of said first latch circuit, a first clock input receiving said asynchronous pulse, a second clock input receiving a synchronous clock signal, a reset input receiving said request signal, and an output providing a synchronous pulse;
a third latch circuit having a data input receiving said synchronous pulse, a set input receiving said request signal, a clock input, and an output providing a synchronous ready signal;
a fourth latch circuit having a data input receiving asynchronous data, an output providing synchronous data, a clock input receiving said synchronous pulse, and a reset input receiving said request signal;
and
pulse timing logic having a first input receiving said synchronous pulse, a second input receiving said clock signal, a third input coupled to said output of said first latch circuit, a fourth input receiving said request signal, and an output coupled to said clock input of said third latch circuit.

3 more elements

A method of operating an adaptive pulse synchronizer for capturing and synchronizing asynchronous information for a digital circuit which provides a request signal, comprising:

asserting, by the adaptive pulse synchronizer, a first logic signal in response to a leading edge of an asynchronous ready signal only when the request signal is provided and keeping the first logic signal asserted while the request signal is provided;
asserting, by the adaptive pulse synchronizer, a second logic signal in response to a trailing edge of the asynchronous ready signal if the first logic signal has been asserted;
providing, by the adaptive pulse synchronizer, a leading edge of a synchronous pulse in response to a clock signal if the second logic signal has been asserted;
providing, by the adaptive pulse synchronizer, a trailing edge of the synchronous pulse in response to the clock signal;
latching, by the adaptive pulse synchronizer, an asynchronous data input to a synchronous data output in response to the synchronous pulse being provided;
and
asserting, by the adaptive pulse synchronizer, a synchronous ready signal after the asynchronous data input is latched to the synchronous data output.

4 more elements

Dependencies are inferred from the claim text.

Adaptive variable length pulse synchronizer

Life of this patent

Adaptive variable length pulse synchronizer

Life of this patent

Abstract

Claims18