Minimizing dynamic crosstalk-induced jitter timing skew
AssigneeDell Products L.P.
InventorsRajen Murugan, Girish K. Singh
Life of this patent
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AssigneeDell Products L.P.
InventorsRajen Murugan, Girish K. Singh
Estimating the term…
A digital signal waveform receiving circuit may be processed by a non-linear adaptive canonical correlation analysis circuit that may quantify and minimize crosstalk-induced jitter timing skew for improving set-up and hold timing margins of data streams on the receiving circuit. A non-linear adaptive canonical correlation analysis circuit may be placed between an incoming digital signal from a serial link and a PHY receiving layer of an information handling system 100. The PHY receiving layer of the information handling system may be coupled to the non-linear adaptive canonical correlation analysis circuit or may be coupled to the digital signal. This coupling selection may be automatically programmed depending on received signal cross-talk-induced jitter timing skew or may be programmed by a user of the information handling system.
An information handling system having a non-linear adaptive canonical correlation analysis circuit for minimizing dynamic crosstalk-induced jitter timing skew of a serial data link, said system comprising:
An information handling system having a non-linear adaptive canonical correlation analysis circuit for minimizing dynamic crosstalk-induced jitter timing skew of a serial data link, said system comprising:
A method for minimizing dynamic crosstalk-induced jitter timing skew of a serial data link with a non-linear adaptive canonical correlation analysis, said method comprising the steps of:
Dependencies are inferred from the claim text.