Device coupled between serial busses using bitwise arbitration

A method of communicating between first and second serial data busses, each bus comprising one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the method comprising:

• transmitting onto the first bus transitions from a first state to a second state, wherein the first and second states are complementary states selected from the dominant and recessive states, each of the transitions signaling the start of a bit on the first bus;
• detecting dominant and recessive states on the first bus at a first predetermined time after each transition and on the second bus at a second predetermined time after each transition, the states representing respective dominant and recessive bits of attempted messages transmitted by nodes of the first and second busses;
• detecting a synchronization signal of the second bus from an alternating current power signal of the second bus;
• transmitting the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on at least one of the first bus and the second bus at the respective first and second predetermined times;
• and
• wherein the transmission of the transition onto the first bus is in response to the synchronization signal of the second bus and causes bits to be transmitted onto the first bus at a slower rate than a maximum bit rate of nodes of the first bus.

An apparatus operable in a data processing arrangement that includes first and second serial data busses, each bus having one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the apparatus comprising:

• a first transceiver coupled to the first bus and capable of transmitting and receiving the dominant and recessive states via the first bus;
• a second transceiver coupled to the second bus and capable of transmitting and receiving the dominant and recessive states via the second bus;
• a synchronization detector coupled to an alternating current power line of the second bus, the synchronization detector providing a synchronization signal proportional to the frequency of the alternating current power line, the synchronization signal signaling the beginning of bit transmissions onto the second bus;
• a processor coupled to the first and second transceivers and the synchronization detector, the processor operable via instructions to cause the apparatus to,
• transmit, via the first transceiver, repeated transitions from a first state to a second state on the first bus in response to the synchronization signal of the second bus, wherein the first and second states are complementary states selected from the dominant and recessive states, and wherein the transmission of the transition onto the first bus in response to the synchronization signal of the second bus causes bits to be transmitted onto the first bus at a slower rate than a maximum bit rate of nodes of the first bus;
• detect via the first transceiver dominant and recessive states on the first bus at a first predetermined time after each transition;
• detect via the second transceiver dominant and recessive states on the second bus at a second predetermined time after each transition;
• and
• transmit the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on either the first bus or the second bus at respective first and second predetermined times.

An apparatus operable in a data processing arrangement that includes first and second serial data busses, each bus having one or more nodes coupled via the respective data bus so that simultaneous transmission on the respective bus of a dominant state by at least one of the nodes and a recessive state by the other nodes results in the dominant state being detectable on the respective bus, the apparatus comprising:

• a first transceiver coupled to the first bus and capable of transmitting and receiving the dominant and recessive states via the first bus;
• a second transceiver coupled to the second bus and capable of transmitting and receiving the dominant and recessive states via the second bus;
• a processor coupled to the first and second transceivers and operable via instructions to cause the apparatus to,
• transmit, via the first transceiver, repeated transitions from a first state to a second state on the first bus, wherein the first and second states are complementary states selected from the dominant and recessive states;
• detect via the first transceiver dominant and recessive states on the first bus at a first predetermined time after each transition;
• detect via the second transceiver dominant and recessive states on the second bus at a second predetermined time after each transition;
• and
• transmit the dominant state on both the first and second bus after the first and second predetermined times if the dominant state was detected on either the first bus or the second bus at respective first and second predetermined times, wherein the first predetermined time is less than a predetermined time after the transition that nodes of the first bus use to detect the state of the first bus.