Communications chip having a plurality of logic analysers
AssigneeSun Microsystems, Inc.
InventorsKnut Tvete, Hans Rygh, Bjorn Dag Johnsen
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Abstract
A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data traffic. There is also a switching matrix for routing data traffic on the chip between the ports. The chip further includes a plurality of logic analyzers. Each logic analyzer is associated with a corresponding one of the ports. Each logic analyzers is operable to monitor data traffic passing through its corresponding port and to trigger on one or more predetermined conditions relating to the monitored data traffic. The chip further includes a control interface to allow reconfiguration of the predetermined conditions for at least one of the logic analyzers.
Claims25
A communications chip comprising:
- a plurality of ports, each port providing an interface for attachment to an external communications facility to exchange data traffic therewith;
- a switching matrix for routing data traffic on the chip between said plurality of ports;
- a plurality of logic analyzers, each logic analyzer being associated with a corresponding one of said plurality of ports, wherein each logic analyzer monitors data traffic passing through its corresponding port and triggers when one or more predetermined conditions relating to the monitored data traffic occurs;
- a control interface, wherein the control interface configures the predetermined conditions and specifies selected fields of header data from packets of the monitored data traffic to be stored when a predetermined condition occurs;
- a multiplexer for each logic analyzer, wherein the multiplexer extracts the selected fields of header data from the packets of the monitored data traffic;
- and
- memory in each logic analyzer, wherein each logic analyzer stores in the memory the selected fields of header data extracted from the packets of the monitored data traffic when the logic analyzer is triggered by the predetermined conditions, wherein each logic analyzer stores in the memory the selected field of header data without storing in the memory other header data.
A method of operating a communications chip having a plurality of ports, each port providing an interface for attachment to an external communications facility to exchange data traffic therewith, and a switching matrix for routing data traffic on the chip between said plurality of ports, said method comprising:
- providing a plurality of logic analyzers, each logic analyzer being associated with a corresponding one of said plurality of ports;
- monitoring with each logic analyzer data traffic passing through its corresponding port;
- triggering within the logic analyzer when one or more predetermined conditions relating to the monitored data traffic occur;
- configuring the predetermined conditions via a control interface on the communications chip;
- specifying, via the control interface, selected fields of header data from packets of the monitored data traffic to be stored when a predetermined condition occurs;
- extracting the selected fields of header data from the packets of the monitored data traffic;
- and
- storing in memory in each logic analyzer the selected fields of header data extracted from the packets of the monitored data traffic when the logic analyzer is triggered by the predetermined conditions, wherein each logic analyzer stores in the memory the selected field of header data without storing in the memory other header data.
A computer readable medium storing instructions that, when executed by a computer, cause the computer to perform a method of operating a communications chip having a plurality of ports, each port providing an interface for attachment to an external communications facility to exchange data traffic therewith, and a switching matrix for routing data traffic on the chip between said plurality of ports, said method comprising:
- providing a plurality of logic analyzers, each logic analyzer being associated with a corresponding one of said plurality of ports;
- monitoring with each logic analyzer data traffic passing through its corresponding port;
- triggering within the logic analyzer when one or more predetermined conditions relating to the monitored data traffic occur;
- configuring the predetermined conditions via a control interface on the communications chip;
- specifying via the control interface selected fields of header data from packets of the monitored data traffic to be stored when a predetermined condition occurs;
- extracting the selected fields of header data from the packets of the monitored data traffic;
- and
- storing in memory in each logic analyzer the selected fields of header data extracted from the packets of the monitored data traffic when the logic analyzer is triggered by the predetermined conditions, wherein each logic analyzer stores in the memory the selected field of header data without storing other header data.
Dependencies are inferred from the claim text.