Frame mapping scheduler for scheduling data blocks using a mapping table and a weight table
AssigneeAgere Systems Inc.
InventorsJinhui Li, Ali A. Poursepanj, Mark Benjamin Simkins
Life of this patent
Estimating the term…
Loading patent…
AssigneeAgere Systems Inc.
InventorsJinhui Li, Ali A. Poursepanj, Mark Benjamin Simkins
Estimating the term…
A network processor or other processing device of a communication system includes scheduling circuitry configured to schedule data blocks for transmission from a plurality of users or other transmission elements in timeslots of a frame. The scheduling circuitry utilizes a weight table and a mapping table. The weight table comprises a plurality of entries, with each of the entries identifying a particular one of the transmission elements. The mapping table comprises at least one entry specifying a mapping between a particular timeslot of the frame and an entry of the weight table. The scheduling circuitry determines a particular transmission element to be scheduled in a given timeslot by accessing a corresponding mapping table entry and utilizing a resultant value to access the weight table.
A processing device for use in a communication system, the device comprising:
A processing device for use in a communication system, the device comprising:
A processing device for use in a communication system, the device comprising:
A processing device for use in a communication system, the device comprising:
A method for use in a processing device of a communication system, the method comprising:
An integrated circuit comprising:
Dependencies are inferred from the claim text.