Clock circuitry for DDR-SDRAM memory controller
AssigneeAtmel Corporation
InventorsAlain Vergnes, Eric Matulik, Frederic Schumacher
Life of this patent
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Abstract
A circuit for providing a delayed clock signal to a synchronous memory controller controlling a synchronous memory device comprises logic delay circuitry for performing synchronous memory device read access, the logic delay circuitry generating delay interval information. A programmable delay line receives a clock signal and the delay interval information, the programmable delay line delaying the clock signal by the delay interval. A 2-input XOR gate receives both the clock signal and the output of the programmable delay line, an output of the XOR gate providing a delayed 2× clock signal.
Claims12
A circuit for providing delayed clock signals to synchronous memory controller, comprising:
- a phased locked loop circuit to generate a faster clock from an original clock signal;
- a logic delay circuit to performing a synchronous memory device read access, the logic delay circuit to generate delay interval information to apply to a control signal sent to a synchronous memory device;
- a programmable delay line to receive the delay interval information from the logic delay circuit and to output a delayed clock signal that has the same frequency and waveform as the clock signal provided to the synchronous memory device, the programmable delay line including an output to provide the delayed clock signal;
- and
- the logic delay circuit to generate a signal delay of a clock period of the clock signal sent to the synchronous memory device.
Dependencies are inferred from the claim text.