Data latch controller of synchronous memory device

#1. Field of the Invention

#The present invention relates to a data input circuit of a synchronous memory device, and more particularly to a data input circuit of a synchronous memory device, in which a data strobe signal can be used for a latch in a state of ensuring a full swing in a ultra high speed synchronous memory device.

#2. Description of the Prior Art

#The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a block diagram of a data input circuit in a memory device for performing a write operation in a 4-bit prefetch scheme;

#FIG. 2 is a waveform illustrating an operation of a data input unit of the memory device in FIG. 1;

#Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

#FIG. 4 is a block diagram of a data input unit in a memory device according to one embodiment of the present invention.

#A data input buffer 400 is a circuit for converting data inputted through a data pin (DQ) to data of a CMOS level. FIG. 4 shows a case in which data are input through one data pin. Accordingly, a memory device including eight data pins may further include seven data input units, each of which is equal to the data input unit in FIG. 4. In this case, it is preferred to commonly use a WDQS buffer 460 and a DQS converter 470 in all data input units.