Semiconductor memory device and arrangement method thereof

A semiconductor memory device comprising:

• a memory cell array comprising sub memory cell array regions, sub word line driver regions arranged on first and second areas between the sub memory cell array regions, and sense amplifier regions arranged on third and fourth areas between the sub memory cell array regions;
• a peripheral circuit region;
• word lines and first local data IO signal lines arranged in the same direction on a first layer above the memory cell array;
• second local data IO signal lines arranged in the same direction as the first local data IO signal lines on a second layer above the memory cell array;
• column selecting signal lines and first global data IO signal lines arranged in a perpendicular direction to the word lines on a third layer above the memory cell array;
• and
• second global data IO signal lines arranged in a perpendicular direction to the first global data IO signal lines on the second layer.

An arrangement method of a semiconductor memory device having a memory cell array comprising sub memory cell array regions, sub word line driver regions arranged on first and second areas between the sub memory cell array regions, sense amplifier regions arranged on third and fourth areas between the sub memory cell array regions, and a peripheral region, the method comprising:

• arranging first local data IO signal lines in the same direction and on the same layer as word lines above the sense amplifier regions;
• arranging second local data IO signal lines in the same direction as the first local data IO signal lines, on a different layer from the word lines above the sense amplifier region;
• arranging column selecting signal lines and first global data IO signal lines in a perpendicular direction to the word lines, on a different layer from the word lines and the second local data IO signal lines above sub memory cell array regions and sense amplifier regions;
• and
• arranging second global data IO signal lines in a perpendicular direction to the first global data IO signal lines, on the same layer as the second local data IO signal lines above the sub memory cell array region and the sub word line driver region.