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US 7,679,980 B2Granted
Resistive memory including selective refresh operation
AssigneeQimonda North America Corp.
InventorsThomas Happ, Jan Boris Philipp
Life of this patent
Estimating the term…
Abstract
A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.
Claims18
A memory comprising:
- an array of phase change memory cells;
- and
- a first circuit for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.
A memory comprising:
- an array of resistive memory cells;
- a sense circuit configured for sensing a state of each memory cell in the array of resistive memory cells;
- a write circuit configured for programming each memory cell in the array of resistive memory cells;
- and
- a controller configured for controlling a refresh operation in which the sense circuit senses the state of each memory cell and the write circuit only refreshes the state of each memory cell sensed to be in a resistance state greater than a lowest resistance state.
2 more elements
A memory comprising:
- an array of phase change memory cells;
- and
- a circuit configured to refresh only memory cells in a non-crystalline state in response to a request for a refresh operation.
Dependencies are inferred from the claim text.