High speed SRAM
AssigneeFronteon Inc
InventorJuhan Kim
Life of this patent
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Abstract
High speed SRAM is realized such that a first dynamic circuit serves as a local sense amp for reading a memory cell through a lightly loaded local bit line, a second dynamic circuit serves as a segment sense amp for reading the local sense amp, and a tri-state inverter serves as an inverting amplifier of a global sense amp for reading the segment sense amp. When reading, a voltage difference in the local bit line is converted to a time difference for differentiating low data and high data by the sense amps for realizing fast access with dynamic operation. Furthermore, a buffered data path is used for achieving fast access and amplify transistor of the sense amps is composed of relatively long channel transistor for reducing turn-off current. Additionally, alternative circuits and memory cell structures for implementing the SRAM are described.
Claims20
A memory device, comprising:
- a memory cell including a pass transistor pair and a cross coupled inverter latch;
- and
- a first dynamic circuit serving as a local sense amp connecting to the memory cell through two local bit lines, wherein the first dynamic circuit includes a pre-charge transistor pair for pre-charging the two local bit lines, a local amplify transistor for reading an output from one of the two local bit lines, where the local amplify transistor is serially connected to a local select transistor, and a write transistor pair for connecting the two local bit lines to a write bit line pair;
- and
- a second dynamic circuit serving as a segment sense amp connecting to the local select transistor through a segment bit line, wherein the second dynamic circuit is composed of a reset transistor for resetting the segment bit line, a segment amplify transistor for reading the segment bit line where the segment amplify transistor is serially connected to a segment select transistor;
- and
- a first tri-state inverter serving as an inverting amplifier of a global sense amp connecting to the segment select transistor through a global bit line, wherein the global sense amp includes a read circuit, a data transfer circuit, a returning buffer and a write circuit;
- and the read circuit includes the first tri-state inverter for reading the global bit line and a pre-set transistor for pre-setting the global bit line;
- and the data transfer circuit includes a second tri-state inverter for bypassing a write data and a read inverter for reading a common node which is connected to the first tri-state inverter and the second tri-state inverter;
- and the write circuit receives the write data and drives the write bit line pair;
- and the returning buffer receives a read output from the read inverter through a returning read path;
- and
- for reducing turn-off current, the local amplify transistor is composed of longer channel length transistor than that of the reset transistor of the segment sense amp, and the segment amplify transistor is composed of longer channel length transistor than that of the pre-set transistor of the global sense amp;
- and
- an output latch circuit receiving and storing an output from the returning buffer;
- and
- a latch control circuit generating a locking signal which is generated by a reference signal based on at least a reference memory cell, in order to lock the output latch circuit.
Dependencies are inferred from the claim text.