Semiconductor memory device utilizing data mask signal for sharing an input/output channel in a test mode and data output method using the same
AssigneeHynix Semiconductor Inc.
InventorKie Bong Ku
Life of this patent
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Abstract
A semiconductor device receives a first data mask signal and a second data mask signal. A data mask control unit outputs a data mask control signal by combining a test mode signal with the first data mask signal. A data clock output unit receives a delay locked loop (DLL) clock and outputs a data clock in response to the data mask control signal. A column address enable (YAE) control signal generating unit generates a column address enable control signal to control the enablement of a column address enable signal. The column address enable control signal generating unit generates the column address enable control signal by combining the test mode signal with the second data mask signal.
Claims24
A semiconductor device receiving a first data mask signal and a second data mask signal, the semiconductor device comprising:
- a data mask control unit outputting a data mask control signal by combining a test mode signal with the first data mask signal;
- a data clock output unit receiving a clock signal and outputting a data clock in response to the data mask control signal;
- and
- a column address enable (YAE) control signal generating unit generating a column address enable control signal by combining the test mode signal with the second data mask signal, wherein the column address enable control signal controls the enablement of a column address enable signal.
A semiconductor device, comprising:
- first and second data pads which read cell data by causing a column address enable signal to be activated when a data read command is applied, wherein the first and second data pads output the read data to outside of a memory, and wherein the output of the read data of one of the first and second data pads is interrupted in response to a first data mask signal;
- a data mask control unit simultaneously controlling the outputs of the first and second data pads in response to the first data mask signal;
- and
- a YAE control signal generating unit generating a column address enable control signal that controls generation of the column address enable signal in response to a second data mask signal.
A data output method of a semiconductor device, comprising the steps of:
- applying a first read command after a test mode is entered into;
- reading data of a memory cell in response to the first read command to transmit the read data to first and second data output pads;
- enabling a first data mask signal to cause the first data output pad to be interrupted when the first read command is applied, such that the first data output pad does not output the read data;
- disabling a column address enable signal in response to a second data mask signal when a second read command is applied such that data of the memory cell is not read again;
- and
- disabling the first data mask signal after the second read command to cause the second data output pad to be interrupted.
Dependencies are inferred from the claim text.