Enhanced erasing operation for non-volatile memory
AssigneeSpansion LLC
InventorsKazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, Hirokazu Nagashima, Kenichi Takehana
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Abstract
Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.
Claims20
A semiconductor device comprising:
- a memory cell array having a plurality of non-volatile memory cells;
- a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array;
- and
- a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage, wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
A method for controlling a semiconductor device, comprising:
- applying a negative voltage to a word line of a memory cell array during an erasing operation of the memory cell array having a plurality of non-volatile memory cells;
- and
- applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage,
- wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
A system for suppressing a capacitive coupling of a word line and a well associated with a memory cell array in a nonvolatile memory device, comprising:
- a negative voltage generating circuit for applying a negative voltage to the word line during an erasing operation of the memory cell array;
- and
- a positive voltage generating circuit for applying a positive voltage to the well when the negative voltage reaches a predetermined voltage,
- wherein there is a timing gap between a start of the applying the negative voltage and a start of the applying the positive voltage.
Dependencies are inferred from the claim text.