Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
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Abstract
A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section. A voltage generating circuit generates a voltage on the basis of the voltage data generated by the arithmetic circuit. The arithmetic circuit, when reading data from the memory cell at threshold level k (k<=n), generates the voltage data by accumulating parameter data at the threshold levels i to k (i<=k).
Claims6
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- and
- a control circuit configured to control a voltage of the word line and the bit line,
- wherein the control circuit supplies a first read voltage to a first word line of the word lines when reading data from a memory cell connected to the first word line, and supplies a second read voltage to a second word line of the word lines when reading data from a memory cell connected to the second word line.
A semiconductor memory device comprising:
- a memory cell configured to store data by a threshold level;
- an arithmetic circuit configured to calculate a voltage data by adding or subtracting first and second parameter data, the first parameter data being data for generating a first level for a first reading or a verify reading, and the second parameter data being data that includes a difference between a second level for a second reading or a verify reading and the first level;
- and
- a voltage generating circuit configured to generate a voltage based on the voltage data calculated by the arithmetic circuit,
- wherein the first parameter is trimmed to a specific value for generating the first level, and the second parameter data is trimmed to a specific value based on the first parameter data trimmed to a specific value and the voltage data calculated by the arithmetic circuit.
Dependencies are inferred from the claim text.