Charge mapping memory array formed of materials with mutable electrical characteristics
AssigneePalo Alto Research Center Incorporated
InventorsWilliam S. Wong, Sanjiv Sambandan, Tse Nga Ng, Robert A. Street
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Abstract
A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.
Claims9
A memory cell array, comprising:
- a data line;
- and
- a component coupled to the data line including a material with a mutable electrical characteristic;
- wherein:
- the component is a first transistor coupled between a first node, a second node, and a third node;
- the third node is the data line;
- and
- further comprising a second transistor coupled between the second node and a fourth node.
A memory cell array, comprising:
- a data line;
- a capacitor;
- and
- a transistor coupled between the data line and the capacitor;
- wherein one of the capacitor and the transistor is a component coupled to the data line including a material with a mutable electrical characteristic.
Dependencies are inferred from the claim text.