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US 7,679,949 B1Granted
Column select multiplexer circuit for a domino random access memory array
OwnerRobert Paul Masleidinventor
Life of this patent
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Abstract
A column select multiplexer circuit for a domino random access memory array including a plurality of column selector circuits for selecting a column from a plurality of columns of static random access memory cells.
Claims9
A column select multiplexer circuit for a domino random access memory array, comprising:
- a plurality of column selector circuits for selecting a plurality of columns of static random access memory cells (SRAM cells), wherein each of said plurality of column selector circuits comprises:
- a bitline precharge circuit for precharging a bitline and a bitline bar of a corresponding column of static random access memory cells (SRAM cells), said bitline precharge circuit coupled to said bitline and said bitline bar;
- a first access n-type field effect transistor (NFET) coupled to said bitline and to a first node for accessing said bitline;
- a second access NFET coupled to said bitline bar and to a second node for accessing said bitline bar;
- a column select line coupled to said first and second access transistors that when activated selects said column of SRAM cells for reading and writing of a selected SRAM cell in said corresponding column of SRAM cells.
2 more elements
A column select multiplexer circuit for a domino random access memory array, comprising:
- a first transistor coupled to a bitline of a first column of static random access memory cells (SRAM cells) and to a bitline precharge line for precharging said bitline;
- a second transistor coupled to a bitline bar of said first column of SRAM cells and to said bitline precharge line for precharging said bitline bar;
- a third transistor cross-coupled to a fourth transistor and coupled between said first and second transistors;
- a first access transistor coupled to said bitline for read/write access of said bitline;
- a second access transistor coupled to said bitline bar for read/write access of said bitline bar;
- and
- a first column select line coupled to said first and second access transistors that when activated selects said first column of SRAM cells from a plurality of columns of SRAM cells each of which are selectable by said column select multiplexer circuit.
4 more elements
Dependencies are inferred from the claim text.