US 7,679,948 B2Granted

Write and read assist circuit for SRAM with power recycling

AssigneeSun Microsystems, Inc.

InventorsHeechoul Park, Song Kim, Lancelot Kwong

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Abstract

A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage level switch, a recycle charge storage, a precharge switch, a write enable switch, and column decoder. The cell voltage level switch is connected to a low power supply and a high power supply and has two states of operation: a write operation state and a read operation state. For each state of operation, the voltage level switch selectively provides a power supply if a column has been selected or if the operation is a read or write. The recycle charge storage stores excess charge from SRAM cells after a read operation or after a write operation in unselected columns. After the read or write operation, the recycle charge storage discharges excess charge to the bitlines during bitline precharging.

Claims20

Dependent claims

A memory circuit, comprising:

(a) a memory array defined by SRAM cells, the memory array having rows and columns, and wordlines for accessing selected rows through a passgate and bitlines for accessing selected columns;
(b) a cell voltage level switch connected to a low power supply and a high power supply, the cell voltage level switch having,
(i) a write operation state defined to selectively provide the low power supply to SRAM cells in columns in which a write operation is to occur, and provide the high power supply to SRAM cells in columns in which the write operation is not identified to occur;
(ii) a read operation state defined to selectively provide the high power supply to SRAM cells in columns in which a read operation is to occur, and provide the high power supply to SRAM cells in columns in which the read operation is not identified to occur;
(c) a recycle charge storage;
(d) a precharge switch connected to the low power supply and to the bitlines of the memory array, the precharge switch being coupled to the cell voltage level switch through the recycle charge storage;
(e) a column decoder for identifying columns selected for the read or write operation state;
and
(f) a write enable switch connected to the cell voltage level switch, the precharge switch, and the column decoder.

6 more elements

A method of writing or reading digital data to SRAM memory cells using charge recycling, comprising the steps of:

(a) selecting column(s) in which a read or write operation is identified to occur, using output from the column decoder;
(b) providing a power supply to SRAM cells through a cell voltage level switch,
(i) the high power supply selectively to SRAM cells in columns in which a read operation is to occur, and selectively provide the high power supply to SRAM cells in columns in which the read operation is not identified to occur;
(ii) the low power supply selectively to SRAM cells in columns in which a write operation is to occur;
(iii) the high power supply selectively to SRAM cells in columns in which the write operation is not identified to occur;
(c) accessing SRAM cells in which a read or write operation is identified to occur, using a wordline to turn on a passgate;
(i) writing digital data into the SRAM cells in which the write operation is to occur;
(ii) reading digital data from SRAM cells in columns in which the read operation is to occur;
(d) storing excess charge in a recycle charge storage when SRAM cells voltages transitions from the high power supply to the low power,
(i) in columns in which the write operation is not identified to occur;
(ii) after the read operation;
and
(e) precharging the bitlines after a read or write operation.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/133,808Filed 5 Jun 2008
Published: US 2009/0303819 A110 Dec 2009
Granted: 16 Mar 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type
G11C 5/147
Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels: voltage…
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C
Static stores