US 7,679,882 B2 · Multilayered chip capacitor and capacitance tunning method of the same

Abstract

There is provided a multilayer chip capacitor capable of tuning capacitance, including: a capacitor body where a plurality of dielectric layers are laminated; a plurality of pairs of first and second internal electrodes arranged alternately, while interposing a corresponding one of the dielectric layers; and a plurality of pairs of first and second external electrodes connected to the first and second internal electrodes, wherein the first and second internal electrodes include a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes, respectively, wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.

Claims9

Dependent claims

A multilayer chip capacitor capable of tuning capacitance, comprising:

a capacitor body where a plurality of dielectric layers are laminated;
a plurality of pairs of first and second internal electrodes arranged alternately such that the internal electrodes of different polarities oppose each other, while interposing a corresponding one of the dielectric layers in the capacitor body;
and
a plurality of pairs of first and second external electrodes formed on a surface of the capacitor body,
wherein the first and second internal electrodes comprise a plurality of groups each including at least one pair of the first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to the pairs of the first and second external electrodes different from one another, respectively,
wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances.

3 more elements

A method of tuning capacitance of a multilayer chip capacitor, the method comprising:

providing a capacitor comprising first and second internal electrodes arranged alternately, while interposing a corresponding one of dielectric layers, and a plurality of first and second external electrodes, wherein the first and second internal electrodes comprise a plurality of groups each including at least one pair of first and second internal electrodes, and the first and second internal electrodes of each of the groups are connected to different pairs of the first and second external electrodes from one another, respectively,
wherein a corresponding one of the pairs of the first and second external electrodes is selectively connected to power lines so that the multilayer chip capacitor has at least two different capacitances;
selecting the first and second external electrodes corresponding to a desired one of the at least two capacitances;
and
mounting the multilayer chip capacitor on a printed circuit board such that the selected first and second external electrodes are connected to the power lines provided on the printed circuit board.

2 more elements

Dependencies are inferred from the claim text.

Multilayered chip capacitor and capacitance tunning method of the same

Life of this patent

Multilayered chip capacitor and capacitance tunning method of the same

Life of this patent

Abstract

Claims9