US 7,679,852 B2 · Adjustment of read/write clock edge timing

Abstract

Apparatus and methods are disclosed that adjust the phase of a read/write clock signal. The read/write clock signal may be used in a data storage apparatus to regulate reading/writing on a data storage media. An apparatus includes an adjustment circuit that adjusts phase of an edge of a read/write clock signal based on the timing of information that is read from a data storage media. Another apparatus includes a servo circuit and a read/write channel circuit. The servo circuit generates a leading edge transition of a servo gate signal in response to a signal indicating that a read/write transducer is approaching a start of a servo wedge. The read/write channel circuit generates a trailing edge transition of the servo gate signal in response to occurrence of a defined time delay following the transducer reading a servo address mark from the servo wedge.

Claims17

Dependent claims

An apparatus comprising:

a read/write channel circuit that generates a trailing edge transition of a servo gate signal based on timing of a servo address mark read from a data storage media;
and
an adjustment circuit that adjusts phase of an edge of a read/write clock signal based on timing of information read from the data storage media, wherein the adjustment circuit adjusts the phase of the edge of the read/write clock signal in response to the trailing edge transition of the servo gate signal based on timing of the servo address mark read from the data storage media.

Dependencies are inferred from the claim text.

Adjustment of read/write clock edge timing

Life of this patent

Adjustment of read/write clock edge timing

Life of this patent

Abstract

Claims17