Solid-state image sensor using junction gate type field-effect transistor as pixel

A camera module comprising:

• a first integrated circuit chip for image sensing which outputs an image signal read by photoelectric conversion of an incident light as a digital signal;
• a second integrated circuit chip for signal processing which receives the digital signal outputted from the first integrated circuit chip and which subjects the digital signal to various types of signal processing to output a digital image signal;
• and
• a lens which is disposed on the first integrated circuit chip and which irradiates a surface of the first integrated circuit chip with light,
• the first integrated circuit chip including:
• a semiconductor substrate;
• and
• a plurality of pixels formed in the semiconductor substrate and each having an accumulation period of signal charges, signal readout period, and discharge period of the signal charges and each including:
• a first semiconductor region of a first conductive type formed in the semiconductor substrate;
• a source region which is formed in a surface region of the first semiconductor region and which is of a second conductive type opposite to the first conductive type;
• a drain region of the second conductive type which is formed apart from the source region in the surface region of the first semiconductor region;
• a second semiconductor region of the first conductive type which is formed in the surface region of the first semiconductor region between the source region and the drain region and to which different voltages are supplied in the accumulation period of the signal charges in the pixel, signal readout period, and discharge period of the signal charges;
• and
• a third semiconductor region of the second conductive type which is formed in the first semiconductor region under the second semiconductor region and electrically connected to the second semiconductor region and which accumulates the signal charges in accordance with an incident light,
• wherein one portion of the drain region is positioned in the surface of the semiconductor substrate.