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US 7,679,458 B2Granted
Ring oscillator for determining select-to-output delay of a multiplexer
AssigneeQUALCOMM Incorporated
InventorKhurram Zaka Malik
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AssigneeQUALCOMM Incorporated
InventorKhurram Zaka Malik
Estimating the term…
The frequency of an oscillating signal generated by a ring oscillator is used to determine the select-to-output delay of standard cell multiplexers. The ring oscillator has no active logic elements other than an odd or even number of standard cell multiplexers. The signal path of the oscillating signal passes through the select input leads of the multiplexers of the ring oscillator. The ring oscillator can be used to characterize how signal propagation delay varies depending on the voltage supplied to the multiplexers. The lowest supply voltage at which a signal can continue to travel through the most critical circuit path of a test circuit can be modeled. In addition, the ring oscillator can be built into operational circuits to monitor timing and signal propagation delay in real time. Real time monitoring of delay enhances the benefits of adaptive voltage scaling, which is used in signal processing circuits in cell phones.
A circuit comprising:
A method comprising:
A method comprising:
A circuit comprising:
An apparatus comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Astable circuits: ring oscillators
Marginal testing, e.g. by varying supply voltage: delay or race condition test, e.g. race hazard test
Testing of digital circuits: clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing…
Pulse technique
Term ended 30 Jul 2026 (estimated)
1. Field
The present disclosure relates generally to oscillator devices and, more specifically, to an oscillator circuit for measuring signal propagation delay through integrated circuits.
2. Background
The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.
FIG. 1 (prior art) is a schematic circuit diagram of a ring oscillator formed from five inverters;
FIG. 2 (prior art) is a schematic circuit diagram of a ring oscillator formed from an even number of ring elements and connected in a differential setup;
Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings.
In accordance with one embodiment, FIG. 4 depicts one implementation of a ring oscillator 20 that includes an even number of ring elements. Ring oscillator 20 has a first multiplexer element 21 and a second multiplexer element 22. The structure of each of first multiplexer element 21 and second multiplexer element 22 is substantially identical. First multiplexer element 21 has a first data input lead 23, a second data input lead 24, a select input lead 25 and an output lead 26. Likewise, second multiplexer element 22 has a first data input lead 27, a second data input lead 28, a select input lead 29 and an output lead 30. Output lead 30 of second multiplexer element 22 is coupled to select input lead 25 of first multiplexer element 21. In this embodiment with two ring elements, output lead 26 of first multiplexer element 21 is coupled directly to select input lead 29 of second multiplexer element 22. In other embodiments described below, output lead 26 of first multiplexer element 21 is coupled to select input lead 29 of second multiplexer element 22 through any number of multiplexer elements that are substantially identical to first and second multiplexer elements 21 and 22.
In this embodiment, first multiplexer element 21 includes two pass gates 31 and 32 and four inverters 33-36. Pass gate 31 is formed with an n-channel field-effect transistor (FET) 37 and a p-channel FET 38. Pass gate 32 is formed with an n-channel field-effect transistor (FET) 39 and a p-channel FET 40. Likewise, second multiplexer element 22 includes two pass gates 41 and 42 and four inverters 43-46. Pass gate 41 is formed with an n-channel field-effect transistor (FET) 47 and a p-channel FET 48. Pass gate 42 is formed with an n-channel field-effect transistor (FET) 49 and a p-channel FET 50.