Semiconductor integrated circuit and method of testing same
AssigneeNEC Electronics Corporation
InventorHayato Ogawa
Life of this patent
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Abstract
A semiconductor integrated circuit includes S PLLs (S is an integer satisfying S≧2), and the (k−1)th PLL 12(k-1) (k is an integer satisfying 2≦k≦S) is connected to the kth PLL 12k in the test mode. In this manner, the examination of S PLLs can be performed in a single test, and thereby it can reduce the time needed to examine PLLs in the semiconductor integrated circuit having a plurality of PLLs.
Claims16
A semiconductor integrated circuit comprising:
- S phase-locked loop circuits (S is an integer satisfying S≧2), the (k−1)th phase-locked loop circuit of the S phase-locked loop circuits being connected to the kth phase-locked loop circuit in series (k is an integer satisfying 2≦k≦S) in a test mode;
- and
- a circuit connected between the (k−1)th phase-locked loop circuit and the kth phase-locked loop circuit in the test mode, and one of frequency-dividing and frequency-multiplying an output clock from the (k−1)th phase-locked loop circuit such that a frequency of a clock inputted to the kth phase-locked loop circuit in a normal mode is the same as a frequency of a clock inputted to the kth phase-locked loop circuit in the test mode.
A semiconductor integrated circuit comprising:
- P phase-locked loop circuit groups (P is an integer satisfying P≧2), each of the phase-locked loop circuit group having S phase-locked loop circuits (S is an integer satisfying S≧2) to which clocks having the same frequency is inputted in a normal mode;
- a first frequency dividing circuit connected in series between the (k−1)th phase-locked loop circuit (k is an integer satisfying 2≦k≦S) and the kth phase-locked loop circuit of the P phase-locked loop circuit groups in a test mode;
- and
- a second frequency dividing circuit connected between the (r−1)th phase-locked loop circuit group (r is an integer satisfying 2≦r≦P) and the rth phase-locked loop circuit group in the test mode,
- wherein the (k−1) phase-locked loop circuit and the kth phase-locked loop circuit are connected in series, and the (r−1)th phase-locked loop circuit group and the rth phase-locked loop circuit group are connected in series,
- wherein the first frequency dividing circuit frequency-divides the output clock from the (k−1)th phase-locked loop circuit such that the resulting frequency is equal to the frequency of an input clock to the kth phase-locked loop circuit operating in the normal mode, and
- wherein the second frequency dividing circuit frequency-divides the output clock from the Sth phase-locked loop circuit of the (r−1)th phase-locked loop circuit group such that the resulting frequency is equal to the frequency of an input clock to the first phase-locked loop circuit of the rth phase-locked loop circuit group operating in the normal mode.
A method of testing a semiconductor integrated circuit comprising S phase-locked loop circuits (S is an integer satisfying S≧2), wherein the (k−1)th phase-locked loop circuit (k is an integer satisfying 2≦k≦S) is connected to the kth phase-locked loop circuit in series, the method comprising:
- inputting a test signal to the phase-locked loop circuit in the most upstream of the semiconductor integrated circuit;
- examining an output clock from a phase-locked loop circuit of the phase-locked loop circuits in the most downstream of the semiconductor integrated circuit;
- and
- one of frequency-dividing and frequency-multiplying an output clock from the (k−1)th phase-locked loop circuit such that a frequency of a clock inputted to the kth phase-locked loop circuit in a normal mode is the same as a frequency of a clock inputted to the kth phase-locked loop circuit in the test mode.
Dependencies are inferred from the claim text.