Low voltage charge pump
AssigneeAtmel Corporation
InventorsJimmy Fort, Fabrice Siracusa
Life of this patent
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Abstract
A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor.
Claims16
A charge pump stage, comprising:
- an NMOS section including a plurality of NMOS transistors connected to a first transfer capacitor coupled between an input node and a first clock input terminal, the first transfer capacitor configured to receive a first clock input signal;
- a first coupling capacitor coupled to a first NMOS gate of a first NMOS transistor and a boost clock signal terminal, the first coupling capacitor configured to receive a boost clock signal;
- a PMOS section that includes:
- a first PMOS transistor coupled between an intermediate node and an output node;
- a second PMOS transistor coupled between a first PMOS gate of the first PMOS transistor and the output node for refreshing a voltage at the first PMOS gate of the first PMOS transistor, the second PMOS transistor having a second PMOS gate coupled to the intermediate node, a second transfer capacitor coupled between the output node and a second inverted clock input terminal, the second transfer capacitor configured to receive an inverted first clock signal;
- a second coupling capacitor coupled between the first PMOS gate of the first PMOS transistor and an inverted boost clock signal terminal, the second coupling capacitor configured to receive an inverted boost clock signal;
- and
- a stabilizing capacitor coupled between the intermediate node and a ground voltage reference.
A multi-stage charge pump, comprising:
- a plurality of charge pump stages connected in series, each charge pump stage including:
- an NMOS section including a plurality of NMOS transistors connected to a first transfer capacitor coupled between an input node and a first clock input terminal, the first transfer capacitor configured to receive a first clock input signal:
- a first coupling capacitor coupled to a first NMOS gate of a first NMOS transistor and a boost clock signal terminal, the first coupling capacitor configured to receive a boost clock signal;
- a PMOS section that includes:
- a first PMOS transistor coupled between an intermediate node and an output node:
- a second PMOS transistor coupled between a first PMOS gate of the first PMOS transistor and the output node for refreshing a voltage at the first PMOS gate of the first PMOS transistor, the second PMOS transistor having a second PMOS gate coupled to the intermediate node, a second transfer capacitor coupled between the output node and a second inverted clock input terminal, the second transfer capacitor configured to receive an inverted first clock signal;
- and
- a second coupling capacitor coupled between the first PMOS gate of the first PMOS transistor and an inverted boost clock signal terminal, the second coupling capacitor configured to receive an inverted boost clock signal, wherein the first clock input signal and the second clock input signal have opposite phases.
Dependencies are inferred from the claim text.