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US 7,679,429 B2Granted
Boost circuit
AssigneeKabushiki Kaisha Toshiba
InventorHiroshi Nakamura
Life of this patent
Estimating the term…
Abstract
A boost circuit includes: first transistors connected in series between a voltage input node and a voltage output node to constitute a charge transfer circuit; and first capacitors, one ends of which are coupled to the respective connection nodes between the first transistors, the other ends thereof being applied with clocks with plural phases, wherein a gate of a certain stage transistor corresponding to one of the first transistors in the charge transfer circuit is coupled to a drain of another stage transistor corresponding to another one of the first transistors, which is disposed nearer to the voltage output node than the certain stage transistor and driven by the same phase clock as that of the certain stage transistor, the certain stage transistor being disposed nearer to the voltage output node than an initial stage transistor.
Claims23
A boost circuit comprising:
- first transistors connected in series electrically between a voltage input node and a voltage output node to constitute a first charge transfer circuit, the first transistors being connected in series along current paths thereof, the first transistors including an initial stage transistor connected to the voltage input node, a second transistor electrically connected in series between the voltage output node and the initial stage transistor, a third transistor electrically connected in series between the voltage output node and the second transistor, an output stage transistor having a source connected to the voltage output node, and a preceding stage transistor having a source connected to a drain of the output stage transistor;
- a fourth transistor having a drain connected to the drain of the output stage transistor;
- a fifth transistor having a drain connected to a source of the fourth transistor;
- first capacitors, one ends of the first capacitors being coupled to the respective connection nodes between the first transistors, the other ends of the first capacitors being applied with clocks with plural phases, the first capacitors including a second capacitor and a third capacitor, one end of the second capacitor being coupled to a drain of the second transistor, and one end of the third capacitor being coupled to a drain of the third transistor;
- a fourth capacitor having one end connected to the source of the fourth transistor and the outer end applied with a third clock;
- and
- a fifth capacitor having one end connected to a source of the fifth transistor and the other end applied with a fourth clock, a phase of the fourth clock being different from a phase of the third clock;
- wherein
- a gate of the second transistor is coupled to the drain of the third transistor, and the other end of the second capacitor is applied with a first clock, the other end of the third capacitor is applied with a second clock, and a phase of the first clock is the same as a phase of the second clock.
6 more elements
A boost circuit comprising:
- first transistors connected in series electrically between a voltage input node and a voltage output node to constitute a first charge transfer circuit, the first transistors being connected in series along current paths thereof, and including an initial stage transistor connected to the voltage input node, a second transistor electrically connected in series between the voltage output node and the initial stage transistor, a third transistor electrically connected in series between the voltage output node and the second transistor, an output stage transistor having a source connected to the voltage output node, and a preceding stage transistor having a source connected to a drain of the output stage transistor;
- a fourth transistor having a drain connected to the drain of the output stage transistor;
- a fifth transistor having a drain connected to a source of the fourth transistor;
- first capacitors, one ends of the first capacitors being coupled to the respective connection nodes between the first transistors, the other ends of the first capacitors being applied with clocks with plural phases, the first capacitors including a second capacitor and a third capacitor, one end of the second capacitor being coupled to a drain of the second transistor, and one end of the third capacitor being coupled to a drain of the third transistor;
- a fourth capacitor having one end connected to the source of the fourth transistor and the outer end applied with a third clock;
- and
- a fifth capacitor having one end connected to a source of the fifth transistor and the other end applied with a fourth clock, a phase of the fourth clock being different from a phase of the third clock;
- wherein a gate of the second transistor is coupled to the drain of the third transistor and the other end of the third capacitor is driven by a first clock, and a phase of the first clock is the same as a phase of a clock driving the other end of the second capacitor.
5 more elements
A boost circuit comprising:
- first transistors connected in series electrically between a voltage input node and a voltage output node to constitute a first charge transfer circuit, the first transistors being connected in series along current paths thereof, and including an initial stage transistor connected to the voltage input node, a second transistor electrically connected in series between the voltage output node and the initial stage transistor, a third transistor electrically connected in series between the voltage output node and the second transistor, an output stage transistor having a source connected to the voltage output node, and a preceding stage transistor having a source connected to a drain of the output stage transistor;
- a fourth transistor having a drain connected to the drain of the output stage transistor;
- a fifth transistor having a drain connected to a source of the fourth transistor;
- first capacitors, one ends of the first capacitors being coupled to the respective connection nodes between the first transistors, the other ends of the first capacitors being applied with clocks with plural phases, the first capacitors including a second capacitor and a third capacitor, one end of the second capacitor being coupled to a drain of the second transistor, and one end of the third capacitor being coupled to a drain of the third transistor;
- a fourth capacitor having one end connected to the source of the fourth transistor and the outer end applied with a third clock;
- and
- a fifth capacitor having one end connected to a source of the fifth transistor and the other end applied with a fourth clock, a phase of the fourth clock being different from a phase of the third clock;
- wherein a gate of a second transistor is coupled to the drain of the third transistor,
- and wherein the first charge transfer circuit has N (where N is an integer equal to 3 or more) transistors corresponding to the first transistors, and wherein
- N−1 capacitors corresponding to the first capacitors are coupled to the respective connection nodes in the first transistors, even numbered capacitors and odd numbered capacitors being driven by clocks with different phases from each other, and wherein
- a gate of i-th transistor (where “i” is an integer smaller than N−2, which is counted from the voltage input node) corresponding to one of the first transistors is coupled to the connection node between (i+1)-th transistor and (i+2)-th transistor.
8 more elements
Dependencies are inferred from the claim text.