Semiconductor device including a bias voltage generator
AssigneeSuVolta, Inc.
InventorDouglas Kerns
Life of this patent
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Abstract
A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator.
Claims29
A semiconductor device, comprising:
- a bias voltage generator including a p-n junction having a first terminal coupled to a first potential and a second terminal that is essentially floating to provide a bias voltage;
- a bias voltage receiving circuit coupled to receive the bias voltage wherein
- the bias voltage receiving circuit includes a first junction field effect transistor (JFET) having a first JFET control gate terminal coupled to receive the bias voltage and the first JFET provides a load for the bias voltage receiving circuit and the bias voltage receiving circuit is a source follower.
A semiconductor device, comprising:
- a first bias voltage generator including a first p-n junction having a first terminal coupled to a first potential and a second terminal that is essentially floating to provide a first bias voltage;
- and
- a first bias receiving circuit formed in close proximity on the semiconductor device to the first bias voltage generator and coupled to receive the first bias voltage wherein
- the p-n junction is included in a junction field effect transistor (JFET);
- the second terminal is a control gate terminal of the JFET;
- and
- the first bias voltage is generated by radiation striking a depletion region formed by the first p-n junction.
A method for creating a bias voltage on a semiconductor device including a p-n junction having a first terminal and a second terminal, comprising the steps of:
- essentially floating the first terminal while applying a potential to the second terminal wherein the first terminal provides the bias voltage wherein
- the first terminal is formed by a control gate for a junction field effect transistor (JFET) and the second terminal is formed by at least a first source/drain region
- wherein the bias voltage is generated by radiation striking a depletion region formed by the p-n junction.
Dependencies are inferred from the claim text.