Reset signal generation circuit
AssigneeFujitsu Microelectronics Limited
InventorsKatsuhiko Sakai, Atsuhiro Sengoku, Teruhiko Saitou
Life of this patent
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Abstract
A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.
Claims12
A reset signal generation circuit for generating a first reset signal provided to a synchronous circuit that operates in accordance with a clock signal, the reset signal generation circuit comprising:
- an operation detection circuit for detecting an operation state of the synchronous circuit and generating an operation detection signal;
- a signal control circuit, connected to the operation detection circuit, for generating the first reset signal that is synchronous or asynchronous to the clock signal based on the operation detection signal;
- an asynchronous circuit responsive to a second reset signal that is asynchronous to the clock signal, wherein the signal control circuit generates the second reset signal based on a system reset signal for resetting the synchronous circuit and the asynchronous circuit;
- and
- a power on reset circuit, connected to the signal control circuit, for generating a power on reset signal for stopping operation of the synchronous circuit and the asynchronous circuit until the power supply voltage reaches a predetermined voltage, wherein the signal control circuit generates the second reset signal in response to the power on reset signal;
- wherein the synchronous circuit generates a control signal, the reset signal generation circuit further comprising:
- a function control circuit for performing or stopping the generation of the first reset signal and the second reset signal that are asynchronous to the clock signal with the signal control circuit based on the control signal and a voltage detection signal.
A reset signal generation circuit for generating a first reset signal provided to a synchronous circuit that operates in accordance with a clock signal, the reset signal generation circuit comprising:
- an operation detection circuit for detecting an operation state of the synchronous circuit and generating an operation detection signal;
- a signal control circuit, connected to the operation detection circuit, for generating the first reset signal that is synchronous or asynchronous to the clock signal based on the operation detection signal;
- an asynchronous circuit responsive to a second reset signal that is asynchronous to the clock signal, wherein the signal control circuit generates the second reset signal based on a system reset signal for resetting the synchronous circuit and the asynchronous circuit;
- and
- a power on reset circuit, connected to the signal control circuit, for generating a power on reset signal for stopping operation of the synchronous circuit and the asynchronous circuit until the power supply voltage reaches a predetermined voltage, wherein the signal control circuit generates the second reset signal in response to the power on reset signal;
- wherein the reset signal generation circuit is connected to a low voltage detection circuit for generating a voltage detection signal, the reset signal generation circuit further comprising:
- an operation control circuit, connected to the low voltage detection circuit, for generating an operation control signal indicating whether or not to stop operation of the low voltage detection circuit.
A reset signal generation circuit for generating a first reset signal provided to a synchronous circuit that operates in accordance with a clock signal, the reset signal generation circuit comprising:
- an oscillation circuit for generating a system clock signal;
- an oscillation control circuit, connected to the oscillation circuit, for determining whether an oscillation stoppage factor that stops oscillation of the oscillation circuit has been eliminated and for starting oscillation of the oscillation circuit when the oscillation stoppage factor has been eliminated;
- a clock generation circuit, connected to the oscillation circuit, for generating the clock signal from the system clock signal;
- an oscillation stabilization control circuit, connected to the oscillation circuit, for controlling a first time period during which oscillation of the oscillation circuit is stabilized;
- a determination circuit, connected to the oscillation stabilization control circuit, for determining whether operation of the oscillation circuit is normal or abnormal after at least the first time period elapses;
- and
- a signal control circuit, connected to the determination circuit, for generating the first reset signal synchronously to the clock signal based on a system reset signal when the determination circuit determines that the operation of the oscillation circuit is normal and for generating the first reset signal asynchronously to the clock signal based on the system reset signal when the determination circuit determines that the operation of the oscillation circuit is abnormal.
Dependencies are inferred from the claim text.