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US 7,679,405 B2Granted
Latch-based sense amplifier
AssigneeAgere Systems Inc.
InventorWilliam B. Wilson
Life of this patent
Estimating the term…
Abstract
Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock.
Claims20
A latch-based sense amplifier, the latch-based sense amplifier comprising:
- an input stage;
- and
- a latch stage, wherein the latch stage is electrically coupled to the input stage, wherein the latch stage includes:
- a third P-type transistor and a fourth P-type transistor;
- a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, and a ninth N-type transistor;
- and
- wherein the gate of the fourth N-type transistor is electrically coupled to the second intermediary signal;
- the gate of the fifth N-type transistor is electrically coupled to the first intermediary signal;
- the source of the fourth N-type transistor, the source of the fifth N-type transistor, the source of the sixth N-type transistor and the source of the seventh N-type transistor are electrically coupled to the lower voltage potential;
- the drain of fourth N-type transistor and the drain of the seventh N-type transistor are electrically coupled to the source of the ninth N-type transistor;
- the drain of fifth N-type transistor and the drain of the sixth N-type transistor are electrically coupled to the source of the eighth N-type transistor;
- the gate of the sixth N-type transistor is electrically coupled to the drain of the ninth N-type transistor, and the gate of the seventh N-type transistor is electrically coupled to the drain of the eighth N-type transistor;
- the gate of the eighth N-type transistor and the gate of the ninth N-type transistor are electrically coupled to the clock signal;
- the drain of the eighth N-type transistor is electrically coupled to the drain of the third P-type transistor, and the drain of the ninth N-type transistor is electrically coupled to the drain of the fourth P-type transistor;
- the gate of the third P-type transistor is electrically coupled to the drain of the fourth P-type transistor, and the gate of the fourth P-type transistor is electrically coupled to the drain of the third P-type transistor;
- and the source of the third P-type transistor and the source of the fourth P-type transistor are electrically coupled to the upper voltage potential.
13 more elements
A differential latch circuit, the circuit comprising:
- an input stage, wherein the input stage provides an interim output during a temporary period relative to a clock signal;
- and
- a latch stage, wherein the latch stage is operable to latch the interim output during the temporary period using the clock signal, and wherein the latch stage includes:
- a fourth N-type transistor, a fifth N-type transistor, a sixth N-type transistor, a seventh N-type transistor, an eighth N-type transistor, and a ninth N-type transistor;
- and
- wherein the gate of the fourth N-type transistor is electrically coupled to the second intermediary signal;
- the gate of the fifth N-type transistor is electrically coupled to the first intermediary signal;
- the source of the fourth N-type transistor, the source of the fifth N-type transistor, the source of the sixth N-type transistor and the source of the seventh N-type transistor are electrically coupled to the lower voltage potential;
- the drain of fourth N-type transistor and the drain of the seventh N-type transistor are electrically coupled to the source of the ninth N-type transistor;
- the drain of fifth N-type transistor and the drain of the sixth N-type transistor are electrically coupled to the source of the eighth N-type transistor;
- the gate of the sixth N-type transistor is electrically coupled to the drain of the ninth N-type transistor, and the gate of the seventh N-type transistor is electrically coupled to the drain of the eighth N-type transistor;
- the gate of the eighth N-type transistor and the gate of the ninth N-type transistor are electrically coupled to the clock signal;
- the drain of the eighth N-type transistor is electrically coupled to the drain of the third P-type transistor, and the drain of the ninth N-type transistor is electrically coupled to the drain of the fourth P-type transistor;
- the gate of the third P-type transistor is electrically coupled to the drain of the fourth P-type transistor, and the gate of the fourth P-type transistor is electrically coupled to the drain of the third P-type transistor;
- and the source of the third P-type transistor and the source of the fourth P-type transistor are electrically coupled to the upper voltage potential.
12 more elements
Dependencies are inferred from the claim text.