Back to results
US 7,679,403 B2Granted
Dual redundant dynamic logic
AssigneeHoneywell International Inc.
InventorDavid O. Erstad
Life of this patent
Estimating the term…
Abstract
A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.
Claims18
A dual redundant logic circuit comprising:
- a precharge circuit that is hardened against single event upset, wherein the precharge circuit comprises four transistors, wherein a first transistor and a second transistor are connected in series to form a first transistor pair, wherein a third transistor and a fourth transistor are connected in series to form a second transistor pair, and wherein the first and second transistor pairs are used to precharge a first output and a second output;
- a first pull down network connected to the precharge circuit, wherein the first pull down network receives a first set of inputs and controls the first output of the dual redundant logic circuit;
- and
- a second pull down network connected to the precharge circuit, wherein the second pull down network receives a second set of inputs substantially the same as the first set of inputs and controls the second output of the dual redundant logic circuit.
1 more element
A dual redundant logic circuit comprising:
- a precharge circuit that is hardened against single event upset, wherein the precharge circuit comprises:
- a first transistor;
- a first precharge node;
- a second transistor connected in series with the first transistor between the first transistor and the first precharge node;
- a second precharge node;
- and
- a third transistor connected in series with the first transistor between the first transistor and the second precharge node, wherein gates of the first, second, and third transistors are connected to a clock input;
- a first pull down network connected to the precharge circuit, wherein the first pull down network receives a first set of inputs and controls the first precharge node of the dual redundant logic circuit;
- and
- a second pull down network connected to the precharge circuit, wherein the second pull down network receives a second set of inputs substantially the same as the first set of inputs and controls the second precharge node of the dual redundant logic circuit.
7 more elements
A method for hardening a dynamic logic circuit comprising:
- hardening a precharge circuit of the dynamic logic circuit, such that the precharge circuit comprises four transistors, wherein a first transistor and a second transistor are connected in series to form a first transistor pair, wherein a third transistor and a fourth transistor are connected in series to form a second transistor pair, and wherein the first and second transistor pairs are used to precharge a first output and a second output of the dynamic logic circuit;
- and
- providing a redundant pull down network, wherein providing a redundant pull down network includes connecting a first pull down network to the precharge circuit and a second pull down network to the precharge circuit, wherein the first pull down network controls the first output and the second pull down network controls the second output.
A method for hardening a dynamic logic circuit comprising:
- hardening a precharge circuit of the dynamic logic circuit, such that the precharge circuit comprises:
- a first transistor;
- a first precharge node;
- a second transistor connected in series with the first transistor between the first transistor and the first precharge node;
- a second precharge node;
- and
- a third transistor connected in series with the first transistor between the first transistor and the second precharge node, wherein gates of the first, second, and third transistors are connected to a clock input;
- and
- providing a redundant pull down network, wherein providing a redundant pull down network includes connecting a first pull down network to the precharge circuit and a second pull down network to the precharge circuit, wherein the first pull down network controls the first precharge node and the second pull down network controls the second precharge node.
6 more elements
Dependencies are inferred from the claim text.