Techniques for precision biasing output driver for a calibrated on-chip termination circuit

An integrated circuit comprising a calibration circuit that controls an on-chip termination resistance in an output driver coupled to a pin, the calibration circuit comprising:

• first transistors coupled in parallel and coupled to the pin, each of said first transistors receiving a different control signal at its gate terminal so as to be selectively controlled;
• a comparator circuit coupled to the pin;
• a counter circuit coupled to receive an output signal of the comparator;
• an adder circuit coupled to receive count signals generated by the counter circuit, wherein the adder circuit is coupled to receive a first input signal, where the first input signal is added to the count signals to generate digital signals;
• and
• a biasing circuit coupled to receive the digital signals generated by the adder circuit and to generate an analog output signal that is used to control the on-chip termination resistance of the first transistors.

A method for calibrating an on-chip termination resistance for an output driver coupled to a pin on an integrated circuit, the method comprising:

• providing on-chip termination resistance using first transistors coupled in parallel to a pin;
• each of said first transistors receiving a different control signal at its gate terminal so as to be selectively controlled;
• monitoring the voltage at the pin using a feedback loop to generate digital signals;
• changing a digital value of the digital signals to generate modified digital signals by receiving a first value and adding the first value to the digital value or subtracting the first value from the digital value;
• converting the modified digital signals to an analog signal;
• and
• setting the on-chip termination resistance of the first transistors in response to the analog signal using second transistors.

An integrated circuit comprising:

• a plurality of transistors coupled to a pin, each of said plurality of transistors receiving a different control signal at its gate terminal so as to be selectively controlled;
• a comparator having a first input coupled to the pin and a second input coupled to a reference voltage;
• a counter having an input coupled to an output of the comparator;
• a biasing circuit to receive a digital count from the counter and to convert the digital count to an analog voltage;
• a plurality of control circuits to enable or disable the plurality of transistors;
• and
• a divider circuit, the divider circuit to receive the analog voltage, divide the analog voltage, and provide the divided analog voltage to one of the plurality of transistors.