High speed integrated circuit

A low noise data transmission circuit, comprising:

• a first data transmission circuit;
• a second data transmission circuit,
• wherein corresponding nodes in the first data transmission circuit and the second data transmission circuit have signals with substantially equal magnitude and opposite phases;
• and
• one or more coupling capacitors operatively coupled between circuit power and circuit ground, wherein the one or more coupling capacitors are configured to cancel charge fluctuations generated by the first data transmission circuit and the second data transmission circuit at the circuit power and circuit ground.

A low noise phase detector circuit, comprising:

• a first phase detector circuit configured to receive a pair of differential input data signals;
• a second phase detector circuit configured to receive a pair of differential input clock signals;
• a control logic configured to generate a pair of differential control signals that control the first and second phase detector circuits;
• wherein corresponding nodes in the first phase detector circuit and the second phase detector circuit have signals with substantially equal magnitude and opposite phases;
• and
• one or more coupling capacitors operatively coupled between circuit power and circuit ground, wherein the one or more coupling capacitors are configured to cancel charge fluctuations generated by the first phase detector circuit and the second phase detector circuit at the circuit power and circuit ground.

A low noise data transmission circuit, comprising:

• an electrostatic discharge (ESD) protection circuit operatively coupled to a pair of pass gate transistors, wherein the pair of pass gate transistors are controlled by a pair of control signals,
• wherein the ESD protection circuit further includes one or more PMOS transistors and one or more NMOS transistors, and substrates of the one or more PMOS transistors and substrates of the one or more NMOS transistors are floating;
• and
• one or more substrate coupling capacitors operatively coupled between substrates of the NMOS transistors and substrates of PMOS transistors, wherein the one or more substrate coupling capacitors are configured to cancel charge fluctuations generated by the low noise data transmission circuit.