Power supply noise resistance testing circuit and power supply noise resistance testing method
AssigneeNEC Corporation
InventorMutsumi Aoki
Life of this patent
Estimating the term…
Abstract
Provided is a power supply noise resistance testing circuit, in which a test pattern is applied to a data input portion of a functional block formed on a semiconductor chip and a voltage on which a power supply noise is superimposed is supplied to a power supply portion of the functional block, thereby testing a power supply noise resistance of the functional block. In the power supply noise resistance testing circuit, a power supply noise generating circuit for generating the power supply noise is provided around or inside the functional block. A power supply of the power supply noise generating circuit is connected with a power supply of the functional block through a connection path to transmit the power supply noise.
Claims16
A power supply noise resistance testing circuit, comprising:
- a power supply noise generating circuit which is provided in one of a peripheral portion and an inner portion of a functional block and includes a power supply portion, for generating a power supply noise, a test pattern being applied to a data input portion of said functional block formed on a semiconductor chip and a voltage superimposing said power supply noise being supplied to a power supply portion of said functional block to test a power supply noise resistance of said functional block, said power supply noise generating circuit being formed on the semiconductor chip;
- and
- a connection path for connecting the power supply portion of the power supply noise generating circuit with a power supply portion of the functional block to transmit said power supply noise.
A power supply noise resistance testing method, comprising:
- supplying a voltage on which a power supply noise generated by a power supply noise generating circuit formed on a semiconductor chip, is superimposed to a power supply portion formed in one of a peripheral portion and an inner portion of said functional block;
- and
- applying a test pattern to a data input portion of said functional block formed on said semiconductor chip to test a power supply noise resistance of said functional block.
Dependencies are inferred from the claim text.