Test equipment and semiconductor device
AssigneeAdvantest Corporation
InventorsDaisuke Watanabe, Toshiyuki Okayasu
Life of this patent
Estimating the term…
Abstract
An interface circuit is connected to an ATE via a test control bus BUS3 that differs from main buses, receives a control signal output from the ATE, and controls multiple BIST circuits according to the control signal. Furthermore, a DUT is configured such that a test result signal specified by the control signal can be read by the ATE via the test control bus. A BISI synchronous control unit generates a first control signal for individually controlling the multiple BIST circuits included in the DUT, and a second control signal for reading the test result signal generated by the BIST circuit, and supplies these signals to the DUT via the test control bus.
Claims17
A test apparatus for a semiconductor device, wherein the semiconductor device includes:
- a plurality of function blocks which input/output signals via a main bus, and which execute predetermined signal processing;
- a plurality of BIST (Built-in Self Test) circuits which are provided in increments of function blocks, and each of which tests the corresponding function block, and generates a test result signal in the form of a digital signal according to the test result;
- and
- an interface circuit which is connected to the test apparatus via a test control bus that differs from the main bus, and which receives a control signal output from the test apparatus, and which is configured such that the interface circuit controls the plurality of BIST circuits according to the control signal, and such that the test result signal specified according to the control signal can be read out via the test control bus by the test apparatus,
- and wherein the test apparatus includes:
- a test unit which transmits/receives signals to/from the semiconductor device via the main bus, and which instructs at least one of the function blocks to execute the predetermined signal processing;
- and
- a control unit which generates a first control signal for individually controlling the plurality of BIST circuits included within the semiconductor device, and a second control signal for reading out the test result signal generated by the BIST circuit from the interface circuit included within the semiconductor device, and which supplies the first control signal and the second control signal to the semiconductor device via the test control bus.
A semiconductor device including:
- a plurality of function blocks which input/output signals via a main bus, and which execute predetermined signal processing;
- a plurality of BIST (Built-in Self Test) circuits which are provided in increments of function blocks, and each of which tests the corresponding function block, and generates a test result signal in the form of a digital signal according to the test result;
- and
- an interface circuit which receives a control signal output from a test apparatus via a test control bus that differs from the main bus, and which is configured such that the interface circuit controls the plurality of BIST circuits according to the control signal, and such that the test result signal specified according to the control signal can be read out via the test control bus by the test apparatus.
Dependencies are inferred from the claim text.