Delay time generation circuit, semiconductor device for protecting secondary batteries using delay time generation circuit, battery pack, and electronic device
AssigneeRicoh Company, Ltd.
InventorTomoyuki Goto
Life of this patent
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Abstract
A delay time generation circuit is disclosed that includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of the last stage or a predetermined stage of the flip-flop circuits of the counter circuit. In the delay time generation circuit, a delay time is generated by the use of an output signal of one of the flip-flop circuits precedent to the last stage or the predetermined stage flip-flop circuit of the counter circuit at testing an electronic circuit. This configuration makes it possible to reduce the delay time without using a special high-speed clock.
Claims13
A delay time generation circuit that includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of a last stage or a predetermined stage of the flip-flop circuits of the counter circuit,
- wherein, at testing an electronic circuit, a delay time is generated by the use of an output signal of only one of the flip-flop circuits precedent to the last stage or the predetermined stage flip-flop circuit of the counter circuit,
- wherein the delay time generation circuit uses as the delay time signal the inverse signal of the output of the last stage or the predetermined stage of the flip-flop circuits of the counter circuit in normal operation, and in a test mode, uses the output signal of only one of the flip-flop circuits preceding the last stage or the predetermined stage flip-flop circuit of the counter circuit, and
- wherein the delay time generation circuit is provided so that an overcharge, an overdischarge, or an overcurrent of a secondary battery is detected to protect the secondary battery from the overcharge, the overdischarge, or the overcurrent, and a detection signal at the detection of the overcharge, the overdischarge, or the overcurrent is delayed by the delay time generation circuit based on the delay signal.
A semiconductor device for protecting a secondary battery that includes a delay time generation circuit so that an overcharge, an overdischarge, or an overcurrent of the secondary battery is detected to protect the secondary battery from the overcharge, the overdischarge, or the overcurrent, wherein
- the delay time generation circuit includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of a last stage or a predetermined stage of the flip-flop circuits of the counter circuit,
- at testing of an electronic circuit, a delay time is generated by the use of an output of only one of the flip-flop circuits preceding the last stage or the predetermined stage flip-flop circuit of the counter circuit, and
- a detection signal at the detection of the overcharge, the overdischarge, or the overcurrent is delayed for a predetermined time with the delay time generation circuit,
- wherein the delay time generation circuit uses as the delay time signal the inverse signal of the output of the last stage or the predetermined stage of the flip-flop circuits of the counter circuit in normal operation, and in a test mode, uses the output signal of only one of the flip-flop circuits preceding the last stage or the predetermined stage flip-flop circuit of the counter circuit.
A battery pack including a semiconductor device for protecting a secondary battery that includes that includes a delay time generation circuit so that an overcharge, an overdischarge, or an overcurrent of the secondary battery is detected to protect the secondary battery from the overcharge, the overdischarge, or the overcurrent, wherein
- the delay time generation circuit includes a counter circuit composed of plural cascade-connected flip-flop circuits for counting a pulse number of an input clock signal and uses as a delay time signal an inverse signal of an output of a last stage or a predetermined stage of the flip-flop circuits of the counter circuit,
- at testing of an electronic circuit, a delay time is generated by the use of an output of only one of the flip-flop circuits preceding the last stage or the predetermined stage flip-flop circuit of the counter circuit, and
- a detection signal at the detection of the overcharge, the overdischarge, or the overcurrent is delayed for a predetermined time with the delay time generation circuit,
- wherein the delay time generation circuit uses as the delay time signal the inverse signal of the output of the last stage or the predetermined stage of the flip-flop circuits of the counter circuit in normal operation, and in the test mode, uses the output signal of only one of the flip-flop circuits preceding the last stage or the predetermined stage flip-flop circuit of the counter circuit.
Dependencies are inferred from the claim text.