Delay time control circuit in a battery protector to reduce delay time
AssigneeNeotec Semiconductor Ltd.
InventorSiarhei Masiuk
Life of this patent
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Abstract
A battery protection IC using charging control pin, Cout, so as to reduce delay time during CP test or FT test for is disclosed. The battery protection IC has a delay time control circuit including a comparator and a delay signal selector. The comparator has a negative input terminal connected to VCC, a positive input terminal connected with the Cout pin and an output terminal connected to the delay signal selector. To perform foregoing test, a voltage source is added to activate the short delay time mode rather than a normal delay time one.
Claims8
A battery protection IC using charging control pin, Cout, to reduce delay time while performing CP test or FT test, is comprising:
- a delay time control circuit having a comparator and a delay signal selector therein, said comparator having a negative input terminal connected to VCC, a positive input terminal connected with said Cout pin and an output terminal connected to said delay signal selector;
- and
- a voltage source connected to said Cout pin so as to activate said delay time control circuit to reduce overcharge delay time while performing said CP test or FT test.
Apparatus having a delay time control circuit in battery protection IC provided for performing FT test or CP test, comprises:
- a resistor;
- a first voltage source;
- a battery cell voltage source;
- a battery protection IC having five pins of VCC, VSS, Vm, Cout, and Dout, a comparator, a delay signal selector, a delay time circuit, an overcharge detector circuit, a control transistor, said comparator having a negative input terminal connected to VCC, a positive input terminal connected with said Cout pin and an output terminal connected to said delay signal selector, said delay signal selector outputs a testing delay signal to said delay time circuit, which permits said overcharge detector circuit to control said control transistor;
- and
- said first voltage source and said resistor are connected in series with said Cout pin and further said cell voltage source with a negative and a positive electrode connected in between said VSS pin and said VCC pin, said first voltage source being provided an adjustable voltage.
Dependencies are inferred from the claim text.